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Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

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Abstract

The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250 nm CMOS process, is presented. The SPS cell provides the latchup protection for standard cells on the principle of power domain control. It is based on a sensing/driving PMOS transistor which acts both as a latchup sensor and a driver for the standard cells, and includes additional PMOS and NMOS transistors for controlling the sensing/driving transistor and interfacing to the external control logic. The previous work has confirmed the SPS cell’s functionality in the case of single event latchup, and the experimental investigation has proven that the SPS cell is immune to single event latchup for LET values up to 74.8 MeV∙cm2/mg. This case study extends the previous research by introducing the circuit-level simulation of the SPS cell’s response to the single event transients (SETs). Using the square pulse current as a SET model, the amplitude and duration of the SET-induced voltage pulses at the SPS cell’s outputs have been analyzed with respect to the injected charge, operating temperature, supply voltage, load (number of standard cells connected to the SPS cell) and sensing/driving transistor’s channel width. The results have shown that the immunity of the SPS cell to SETs can be significantly enhanced by connecting a larger number of standard cells to the SPS cell and increasing the sensing/driving transistor’s size, without any area overhead. An analytical expression for calculating the critical charge in terms of the transistor size and the number of standard cells connected to the SPS cell has been derived. Moreover, the SPS cell can be used as a SET sensor for detecting the levels of injected charge which cannot be mitigated by the increase of transistor size and load, and in conjunction with the external control logic it could be possible to measure the SET duration and perform online corrections of the SET-induced faults in the standard cells supplied by the SPS cell.

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Acknowledgments

This work was conducted within the bilateral project between the IHP GmbH and the Faculty of Electronic Engineering, University of Nis. The project has been funded jointly by the German Academic Exchange Service (DAAD - Deutscher Akademischer Austausch Dienst) and the Ministry of Education, Science and Technological Development of the Republic of Serbia.

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Authors and Affiliations

  1. Faculty of Electronic Engineering, University of Niš, Niš, Serbia

    Marko S. Andjelković, Goran S. Ristić & Goran S. Jovanović

  2. IHP GmbH, Frankfurt (Oder), Germany

    Vladimir Petrović & Zoran Stamenković

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  1. Marko S. Andjelković
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  2. Vladimir Petrović
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  3. Zoran Stamenković
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  4. Goran S. Ristić
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  5. Goran S. Jovanović
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Correspondence to Marko S. Andjelković.

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Responsible Editor: S. Hellebrand

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Andjelković, M.S., Petrović, V., Stamenković, Z. et al. Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch. J Electron Test 31, 275–289 (2015). https://doi.org/10.1007/s10836-015-5529-1

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