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Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection

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An Erratum to this article was published on 15 December 2015

Abstract

Today’s Integrated Circuit (IC) industry is suffering from piracy, overbuild ICs, and hardware Trojans. One way to protect ICs is logic locking. Logic locking is done by inserting extra logic to the original design’s netlist such that correct outputs are produced only when the correct key is applied. However, the determination of locations to insert logic is a computationally expensive process. In this paper, we propose a fault emulation technique to speed up the process of determination of fault locations. Our fault emulation technique enables dynamic multiple fault injection as well as real-time fault impact computation in a single FPGA configuration. The effectiveness of the proposed emulation technique is evaluated with ISCAS’89 sequential benchmark circuits and results are presented.

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Authors and Affiliations

  1. Department of Computer Engineering, Yeditepe University, Istanbul, Turkey

    Sezer Gören, Cemil Cem Gürsoy & Abdullah Yildiz

Authors
  1. Sezer Gören
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  2. Cemil Cem Gürsoy
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  3. Abdullah Yildiz
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Corresponding author

Correspondence to Sezer Gören.

Additional information

Responsible Editor: M. Tehranipoor

This project is supported by the Scientific and Technological Research Council of Turkey (TUBITAK), under contract EEEAG/114E022.

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Gören, S., Gürsoy, C.C. & Yildiz, A. Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. J Electron Test 31, 525–536 (2015). https://doi.org/10.1007/s10836-015-5544-2

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  • DOI: https://doi.org/10.1007/s10836-015-5544-2

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