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Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests

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Abstract

The objective of this work is to minimize testing cost of analog and RF circuits for which complete specification tests are available. We use an integer linear program (ILP) to eliminate as many tests as possible without exceeding the required defect level. The method leverages correlation among specifications, thereby avoiding the tests for specifications that are sufficiently covered by tests for other specifications. First, Monte Carlo simulation determines probabilities for each test covering all other specifications it was not originally intended for. These probabilities and the given defect level then define an ILP model for eliminating unnecessary tests. An hypothetical example illustration of ten specifications demonstrates that depending on the defect level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications followed by ILP optimization for two commercially available integrated circuits, an operational amplifier and a radio frequency power controller (RFPC), are presented as evidence of effectiveness of the technique.

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Acknowledgments

The authors thank Dr. R. A. Parekhji for suggesting the problem of specification based test minimization and for his interest in this work. This research is supported in part by the National Science Foundation Grants CNS-0708962, CCF-1116213 and IIP-0738088.

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Authors and Affiliations

  1. Intel Corporation, Hillsboro, OR, 97124, USA

    Suraj Sindia

  2. ECE Department, Auburn University, Auburn, AL, 36849, USA

    Vishwani D. Agrawal

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  1. Suraj Sindia
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  2. Vishwani D. Agrawal
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Correspondence to Vishwani D. Agrawal.

Additional information

Responsible Editor: L. M. Bolzani Pöhls

Work described here was performed while S. Sindia was with the Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849, USA. Ideas in this research were first presented at the 15th IEEE Latin-American Test Workshop, Fortaleza, Brazil, March 12-15, 2014 [22].

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Sindia, S., Agrawal, V.D. Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J Electron Test 31, 479–489 (2015). https://doi.org/10.1007/s10836-015-5545-1

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  • DOI: https://doi.org/10.1007/s10836-015-5545-1

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