Skip to main content
Log in

Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits

Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Due to the intrinsic lack of restoring paths, dynamic logic circuits have significant single-event susceptibility, and thus, they are not preferred in applications requiring high reliability when compared to static logic. However, in high speed applications, this circuit family is still very attractive. This papers presents two layout-based single-event resilient dynamic logic designs. The resultant SET pulse is suppressed because of charge-sharing in the layout-level. Simulation results verify that they enjoy higher single event tolerance. Experimental results validate the fact that approximately 20 ~ 30 % of magnitude reduction in cross-section is achieved in both designs. On the other hand, the increase in single-event performance is achieved at the expense of power and area overheads of 10 and 15 %, respectively, using our layout style in 130 nm CMOS bulk technology.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Ahlbin J, Massengill L (2009) Single-event transient pulse quenching in advanced CMOS logic circuits. IEEE Trans Nucl Sci 56(6):3050–3056

    Article  Google Scholar 

  2. Atkinson NM, Witulski AF, Holman WT, Ahlbin JR, Bhuva BL, Massengill LW (2011) Layout technique for single-event transient mitigation pulse quenching. IEEE Trans Nucl Sci 58(3):885–890

    Article  Google Scholar 

  3. Black JD, Sternberg AL, Alles ML, Witulski AF, Bhuva BL, Massengill LW, Benedetto JM, Baze MP, Wert JL, Hubert MG (2005) HBD layout isolation techniques for multiple node charge collection mitigation. IEEE Trans Nucl Sci 52(6):2536–2541

    Article  Google Scholar 

  4. Calin T, Nicolaidis M, Velazco R (1996) Upset hardenedmemory design for submicronCMOS technology. IEEE Trans Nucl Sci 43(6):2874–8

    Article  Google Scholar 

  5. Chen J, Chen S, He Y, Chi Y, Qin J, Liang B, Liu B (2012) Novel layout technique for N-Hit single-event transient mitigation via source-extension. IEEE Trans Nucl Sci 59(6):2859–2866

    Article  Google Scholar 

  6. Narasimham B, Gambles JW, Shuler RL, Bhuva BL, Massengill LW (2008) Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread. IEEE Trans Nucl Sci 55(6):3456–3460

    Article  Google Scholar 

  7. She X, Li N, Erstad DO (2012) SET tolerant dynamic logic. IEEE Trans Nucl Sci 59(2):434–438

    Article  Google Scholar 

  8. SIA (2001) The international technology roadmap for semiconductors. [Online]. Available: http://www.itrs.net/Links/2001ITRS/Design.pdf

  9. Wang H-B, Li M-L, Chen L, Liu R, Baeg S, Wen S-J, Wong R, Fung R, Bi J-S (2014) Single event resilient dynamic logic designs. J Electron Test 30(6):751–761

    Article  Google Scholar 

Download references

Acknowledgments

This project is in part supported by NSFC under contract No. 61504038.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Haibin Wang.

Additional information

Responsible Editor: V. D. Agrawal

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wang, H., Li, M., Dai, X. et al. Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits. J Electron Test 32, 97–103 (2016). https://doi.org/10.1007/s10836-015-5559-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-015-5559-8

Keywords

Navigation