Abstract
Addition is one of the fundamental arithmetic operations which are used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. In this paper, the Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) is constructed, which is efficient in terms of accuracy, power and area. While considering the elementary structure of an image processing applications, it is a combination of the multipliers and delays, which in turn are the combination of the adders. This research paper describes the Algorithmic strength reduction technique which leads to a reduction in hardware complexity by exploiting the significances. This transformation is basically implemented for the reduction in the power consumption and area efficient of Very Large Scale Integration (VLSI) design or iteration period in a programmable Digital Signal Processing (DSP) implementation. The significance approximation error tolerant adder is designed using full adder and approximate full adder cells with reduced complexity at the gate level. The performance of 16 bit conventional Carry Select Adder (CSLA), 16 bit Error Tolerant carry select Adder (ET-CSLA) and proposed Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) are compared. For all the 216 input combinations, comparison is made between existing and proposed CSLA adders and the error tolerance analysis is carried out for accuracy improvement. Application of image processing is carried out using proposed SAET-CSLA.
Similar content being viewed by others
References
Gupta V, Mohapatra D, Park SP, Raghunathan A, Roy K (2011) IMPACT: imprecise adders for low-power approximate computing. Proc IEEE/ACM Int Symp Low-Power Electron Des 409–414
He Y, Chang CH, Gu J (2005) An area efficient 64-bit square root carry-select adder for low power applications. Proc IEEE Int Symp Circ S 4:4082–4085
Hegde R, Shanbhag N (1999) Energy-efficient signal processing via algorithmic noise-tolerance. Proc IEEE/ACM Int Symp Low Power Electron Des 30–35
Jayanthi AN, Ravichandran CS (2012) Design of error tolerant adder. Am J Appl Sci 9(6):818–824
V Muralidharan, M Jagadeeswari (2012) An enhanced Carry elimination adder for low power VLSI applications. Int J Eng Res Appl 2(2) 1477–1482
Neeharika R, Venkanna, Kavitha M (2012) Design of low-power high-speed truncation-error tolerant adder and its application in digital signal processing. Int Eng Res Appl 2(2):939–944
Parhi KK (2007) VLSI digital signal processing systems: design and implementation, 255–279, Wiley
Rawat K, Darwish T, Bayoumi M (2002) A low power and reduced area Carry select adder. Proc 45th Midwest Symp Circuit 1:467–470
Saeed V (2007) Vaseghi. Wiley, Multimedia Signal Processing
Saxena P, Purohit U, Joshi P (2013) Analysis of low power, area- efficient and high speed fast adder. Int J Adv Res Comput Commun Eng 2(9):356–375
Shim B, Sridhara S, Shanbhag N (2004) Reliable low-power digital signal processing via reduced precision redundancy. Proc IEEE Trans VeryLarge Scale Integr Syst 12(no. 5):497–510
Singh S, Kumar D (2011) Design of area and power efficient modified carry select adder. Int J Comput Appl 33(No. 3):975–987
Varatkar G, Shanbhag N (2006) Energy-efficient motion estimation using error-tolerance. Proc IEEE/ACM Int Symp Low Power Electron Des 113–118
Yadav S, Mehra R (2014) Analysis of FPGA based recursive filter using optimization techniques for high throughput. Int J Adv Res Technol 3:341–343
Kim Y, Kim L-S (2001) A low power carry select adder with reduced area. Proc IEEE Int Symp Circ S 4:218–221
Zhu N, Goh WL, Yeo KS (2009) An enhanced low-power highspeed adder for error-tolerant application. Proc IEEE Int Symp Integr Circuits 69–72
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: V. D. Agrawal
Rights and permissions
About this article
Cite this article
Jothin, R., Vasanthanayaki, C. High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications. J Electron Test 32, 377–383 (2016). https://doi.org/10.1007/s10836-016-5587-z
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-016-5587-z