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Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering

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Abstract

Modern FPGAs have a great market share in hardware prototyping, massive parallel systems and reconfigurable architectures. Although the field-programmability of FPGAs is an effective feature in the growth and diversity of their applications; it has caused security concerns for IPs/Designs on FPGAs. Recent researches show that a reliable mechanism is required to protect the IPs/applications on FPGAs against malicious manipulations during all stages of design lifecycle, especially when they are operating in the field. In this paper, we propose a new tamper-resistant design methodology (Security Path methodology) and a revised security-aware FPGA architecture. This methodology protects the configured design against tampering attacks in parallel with the normal operation of the circuit. When the attack is discovered, the normal data flow is obfuscated and the circuit is blocked. Experimental results show that this methodology provides near full coverage in tampering detection with overhead of 12.32 % in power, 12 % in delay and 38 % in area.

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Correspondence to Ali Jahanian.

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Responsible Editor: M. Tehranipoor

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Zamanzadeh, S., Jahanian, A. Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering. J Electron Test 32, 329–343 (2016). https://doi.org/10.1007/s10836-016-5593-1

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  • DOI: https://doi.org/10.1007/s10836-016-5593-1

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