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Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

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Abstract

This paper presents a flexible runs-aware PRL coding method whose coding algorithm is simple and easy to implement. The internal 2-n-PRL coding iteratively codes 2n runs of compatible or inversely compatible patterns inside a single segment. The external N-PRL coding iteratively codes flexible runs of compatible or inversely compatible segments across multiple segments. The decoder architecture is concise. The benchmark circuits verify the flexible runs-aware PRL coding method, the experimental results show it obtains higher compression ratio and shorter test application time.

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Acknowledgment

This research work was supported by the National Natural Science Foundation of China (61001049, 61372149 and 61370189) and Scholarship sponsored by China Scholarship Council [2013] 3018.

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Correspondence to Haiying Yuan.

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Responsible Editor: K. Chakrabarty

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Yuan, H., Ju, Z., Sun, X. et al. Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding. J Electron Test 32, 639–647 (2016). https://doi.org/10.1007/s10836-016-5595-z

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  • DOI: https://doi.org/10.1007/s10836-016-5595-z

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