Abstract
Manufacturing of core based three-dimensional (3D) integrated circuit (IC) is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced power consumption. But due to scaling in technology features these chips are more complex. Hence testing of these 3D ICs is a challenging task and designing the test wrapper of core is also an important issue in this respect. This paper follows a IEEE 1500-style wrapper design for 3D ICs using Through Silicon Vias (TSVs) for testing purpose. It is assumed that the core elements are distributed over several layers of the ICs. As the number of available TSVs are limited due to small chip area, this work is intended to design balanced wrapper chains using minimum number of TSVs so that testing time of a core is reduced. In this work we have proposed a polynomial time algorithm of O(N) to design the test wrapper. The results are presented based on the ITC’02 SOC test benchmarks and compared with prior works. Obtained results show that our algorithm provides better utilization of TSVs compared to the work presented in Noia et al. (2011).
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Roy, S.K., Giri, C. & Rahaman, H. Optimization of Test Wrapper for TSV Based 3D SOCs. J Electron Test 32, 511–529 (2016). https://doi.org/10.1007/s10836-016-5610-4
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DOI: https://doi.org/10.1007/s10836-016-5610-4