Skip to main content
Log in

Analog Circuit Test Point Selection Incorporating Discretization-Based Fuzzification and Extended Fault Dictionary to Handle Component Tolerances

Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Analog circuit test point selection aims to find the least number of test points that can isolate all the fault modes (including the fault-free case). The fault dictionary, which uses the integer-valued codes to represent the diagnosability of a specific test point, is very popular and saves computation efforts. However, the classical fault dictionary has a limited ability to handle the component tolerances and continuous-valued monitoring variables. To solve the problem, the approach of clustering-based discretization (CBD) is used to abstract the information of data samples distribution. We also develop a new fault dictionary construction technique called extended fault dictionary (EFD). An element of EFD is a set containing either a single integer code or multiple integer codes. The fault isolation rules are redefined, and a novel entropy measure is created in line with CBD of the continuous values. The practical test point selection procedures are presented, which avoids the likelihood to include a redundant test point. Finally, two application studies of circuit test point election are presented, showing that the proposed method provides an effective implementation option for the engineering practice of circuit diagnosis.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Abbreviations

EFD:

Extended fault dictionary

CUT:

Circuit under test

CBD:

Clustering-based discretization

DBC:

Density-based clustering

FMF:

Fuzzy membership function

ASFE:

Fuzzy entropy by ambiguity sets

F :

Set of candidate fault modes (including the fault-free case)

L :

Total number of fault modes

f l :

The kth fault mode with l = 1 , 2 ,  ⋯  , L

T :

Set of candidate test points

M :

Total number of test points

t i :

The ith test point (dimension) with i = 1 , 2 ,  ⋯  , M

X i :

One-dimensional data set corresponding to t i

N :

Total number of data pieces

x iu :

The uth data sample in X i with u = 1 , 2 ,  ⋯  , N

τ u :

The uth label in the label vector corresponding to the uth data sample with u = 1 , 2 ,  ⋯  , N

Λ i :

Set of clusters for the ith dimension with i = 1 , 2 ,  ⋯  , M

J i :

Total number of clusters for the ith dimension

Q ij :

The jth cluster in Λ i with j = 1 , 2 ,  ⋯  , J i

\( {\tilde{Q}}_{ij} \) :

FMF corresponding to Q ij

Ξ ij :

Set of data samples belonging to Q ij

m ij :

Center of the data samples belonging to Q ij

D ij :

Width of the data samples belonging to Q ij

μ Q (x):

Membership degree under fuzzy set Q

\( SD\left(\left.{Q}_{ij}\right|{f}_l\right) \) :

Conditional sub-degree with \( {Q}_{ij} \) based on f l

\( {\varTheta}_{f_l}\left({X}_i\right) \) :

Set of elements in X i whose fault mode label is f l

E = [e li ] L × M :

EFD for the circuit under test

ε :

Confident threshold

T opt :

Present set of optimal test points

T comb :

Present set of a specific test points combination

P :

Total number of ambiguity sets in accordance with T comb

A p :

The pth ambiguity set in accordance with T comb where p = 1 , 2 ,  ⋯  , P

\( SD\left({Q}_{ij}|{A}_p\right) \) :

Conditional sub-degree with \( {Q}_{ij} \) based on A p

\( {\varOmega}_{A_p}\left({X}_i\right) \) :

Set of elements in X i whose fault mode (i.e. label) is contained in A p

\( ASF{E}_i\left({Q}_{ij}|{A}_p\right) \) :

conditional ASFE associated with A p for test point t i

ASFE i :

Total ASFE for test point t i

t opt :

Optimal test point among the remaining candidate test points

References

  1. Abderrahman A, Kaminska B, Cerny E (1996) Optimization-based multifrequency test generation for analog circuits. J Electron Test 9:59–73

    Article  Google Scholar 

  2. Bilski P, Wojciechowski JM (2007) Automated diagnostics of analog systems using fuzzy logic approach. IEEE Trans Instrum Meas 56:2175–2185

    Article  Google Scholar 

  3. Catelani M, Fort A, Alippi C (2002) A fuzzy approach for soft fault detection in analog circuits. Measurement 32:73–83

    Article  Google Scholar 

  4. Chang YH (2002) Frequency–domain grouping robust fault diagnosis for analog circuits with uncertainties. Int J Circuit Theory Applications 30:65–86

    Article  MATH  Google Scholar 

  5. Cui Y, Shi J, Wang Z (2015) An analytical model of electronic fault diagnosis on extension of the dependency theory. Reliab Eng Syst Saf 133:192–202

    Article  Google Scholar 

  6. Frank E, Witten IH (1998) Generating accurate rule stes without global optimization. Proceedings of the 15th Internatinal Conference Machine Learning (ICML '98), 144--151

  7. Golonek T, Rutkowski J (2007) Genetic-algorithm-based method for optimal analog test points selection. IEEE Trans Circuits Syst II: Express Briefs 54:117–121

    Article  Google Scholar 

  8. Hochwald W, Bastian JD (1979) A DC approach for analog fault dictionary determination. IEEE Trans Circuits Syst 26:523–529

    Article  Google Scholar 

  9. Horn D, Gottlieb A (2001a) The method of quantum clustering. Adv Neural Inf Proces Syst 14:769–776

    Google Scholar 

  10. Horn D, Gottlieb A (2001b) Algorithm for data clustering in pattern recognition problems based on quantum mechanics. Phys Rev Lett 88(1):261--268

  11. K.B. Irani, (1993) Multi-interval discretization of continuous-valued attributes for classification learning, Proc. 13th International Joint Conference on Artificial Intelligence, pp. 1022–1027

  12. Jiang R, Wang H, Tian S, Long B (2010) Multidimensional fitness function DPSO algorithm for analog test point selection. IEEE Trans Instrum Meas 59:1634–1641

    Article  Google Scholar 

  13. Lei H, Qin K (2013) Quantum-inspired evolutionary algorithm for analog test point selection. Analog Integr Circ Sig Process 75:491–498

    Article  Google Scholar 

  14. Lei H, Qin K (2014) Greedy randomized adaptive search procedure for analog test point selection. Analog Integr Circ Sig Process 79:371–383

    Article  Google Scholar 

  15. Lei H, Qin K (2015) A general method for analog test point selection using multi-frequency analysis. Analog Integr Circ Sig Process 84:185

    Article  Google Scholar 

  16. Lin P, Elcherif Y (1985) Analogue circuits fault dictionary—new approaches and implementation. Int J Circuit Theory Applications 13:149–172

    Article  Google Scholar 

  17. Manetti S, Piccirilli M, Liberatore A (1990) Automatic test point selection for linear analog network fault diagnosis, Proc. IEEE international symposium on circuits and systems, pp. 25–28

  18. Pecht M, Jaai R (2010) A prognostics and health management roadmap for information and electronics-rich systems. Microelectron Reliab 50:317–323

    Article  Google Scholar 

  19. Pinjala KK, Kim BC (2003) An approach for selection of test points for analog fault diagnosis. Proc. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 287–294

  20. Prasad V, Babu N (2000) Selection of test nodes for analog fault diagnosis in dictionary approach. IEEE Trans Instrum Meas 49:1289–1297

    Article  Google Scholar 

  21. Ram RB, Moorthy VP, Devarajan N (2009) Fuzzy based time domain analysis approach for fault diagnosis of analog electronic circuits, Proc. IEEE International Conference on Control, Automation, Communication and Energy Conservation, pp. 1–6

  22. Sheppard JW, Butcher SG (2007) A formal analysis of fault diagnosis with D-matrices. J Electron Test 23:309–322

  23. Starzyk JA, Nelson DE, Sturtz K (2000) A mathematical foundation for improved reduct generation in information systems. Knowl Inf Syst 2:131–146

    Article  MATH  Google Scholar 

  24. Starzyk J, Liu D, Liu Z-H, Nelson DE, Rutkowski JO (2004) Entropy-based optimum test points selection for analog fault dictionary techniques. IEEE Trans Instrum Meas 53:754–761

    Article  Google Scholar 

  25. Stenbakken GN, Souders TM (1987) Test-point selection and testability measures via QR factorization of linear models. IEEE Trans Instrum Meas 1001:406–410

    Article  Google Scholar 

  26. Tadeusiewicz M, Hałgas S, Korzybski M (2012) Multiple catastrophic fault diagnosis of analog circuits considering the component tolerances. Int J Circuit Theory Applications 40:1041–1052

    Article  Google Scholar 

  27. Van Spaandonk J, Kevenaar TA, (1996) Iterative test-point selection for analog circuits. Proceedings of 14th VLSI Test Symposium, 1996., IEEE, pp. 66–71

  28. Vichare NM, Pecht MG (2006) Prognostics and health management of electronics. IEEE Trans Compon Packag Technol 29:222–229

    Article  Google Scholar 

  29. Wang P, Yang S (2005) A new diagnosis approach for handling tolerance in analog and mixed-signal circuits by using fuzzy math. IEEE Trans Circuits Syst I: Regular Papers 52:2118–2127

    Article  MathSciNet  Google Scholar 

  30. Yang C, Tian S, Long B (2009) Application of heuristic graph search to test-point selection for analog fault dictionary techniques. IEEE Trans Instrum Meas 58:2145–2158

    Article  Google Scholar 

  31. Yang C, Tian S, Long B, Chen F (2010) A test points selection method for analog fault dictionary techniques. Analog Integr Circ Sig Process 63:349–357

    Article  Google Scholar 

  32. Yang C, Tian S, Long B, Chen F (2011) Methods of handling the tolerance and test-point selection problem for analog-circuit fault diagnosis. IEEE Trans Instrum Meas 60:176–185

    Article  Google Scholar 

  33. Zhao D, He Y (2015a) A new test points selection method for analog fault dictionary techniques. Analog Integr Circ Sig Process 82:435–448

    Article  Google Scholar 

  34. Zhao D, He Y (2015b) Chaotic binary bat algorithm for analog test point selection. Analog Integr Circ Sig Process:1–14

  35. Zhao D, He Y (2015) A new test point selection method for analog circuit. J Electron Test 31:53–66

Download references

Acknowledgments

The authors express sincere appreciation to the editor and reviewers for their efforts to improve this paper. This work is sponsored by fund project Z132014B002.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yiqian Cui.

Additional information

Responsible Editor: B. C. Kim

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Cui, Y., Shi, J. & Wang, Z. Analog Circuit Test Point Selection Incorporating Discretization-Based Fuzzification and Extended Fault Dictionary to Handle Component Tolerances. J Electron Test 32, 661–679 (2016). https://doi.org/10.1007/s10836-016-5620-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-016-5620-2

Keywords

Navigation