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A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

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Abstract

In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) in which irregular Mesh-based and fault tolerant NoCs that are using Table-based routing. The proposed approach encompasses TPG and TRA located in the Network Adapter (NA) as well as a Packet Comparing Module (PCM) embedded in the routers. The approach, in addition, with a high scalability leads to 100% Test Coverage (TC) and 82.3% capability of diagnosing faulty channels in NoCs with a high scale. Furthermore, the approach is capable of being performed within one Round (two phase) run with a total time of 70 clocks which is considered as cost-effective compared with the preceding methods. The simulation results demonstrate that the hardware cost of PCM is trivial compared with the hardware of RASoC, HERMES, Æthereal and Vici routers.

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Babak Aghaei & Midia Reshadi

  2. Telecommunication Research Center, Tehran, Iran

    Ahmad Khademzadeh & Kambiz Badie

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  1. Babak Aghaei
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  2. Ahmad Khademzadeh
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  3. Midia Reshadi
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  4. Kambiz Badie
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Correspondence to Kambiz Badie.

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Responsible Editor: X. Li

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Aghaei, B., Khademzadeh, A., Reshadi, M. et al. A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip. J Electron Test 33, 501–513 (2017). https://doi.org/10.1007/s10836-017-5666-9

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