Abstract
Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.
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References
Aitken R (2015) Designing SoCs with planar fully depleted devices and FinFETs. Keynote speech-International Electron Device Meeting, USA
Alioto M (2010) Analysis of layout density in FinFET standard cells and impact of fin technology. IEEE international Symposium on circuits and systems (ISCAS’10), pp 3204-3207
M. Alioto, Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(5):751–762, 2011
Bhattacharya D et al (2014) FinFETs: from devices to architectures. Advances in Electronics, ID 365689:21
Chang L et al (2003) Extremely scaled silicon nano-CMOS devices. In Proceedings of the IEEE 91(11):1860–1873
Colinge J-P (2008) FinFET and other multi-gate transistor. Springer
Dunga M et al (2008) BSIM-CMG: a compact model for multi-gate transistors. Springers US
Engelke P et al (2008) On detection of resistive bridging defects by low-temperature and low-voltage testing. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(2):327–338
Fenouillet-Beranger C et al (2004) Requirements for ultra-thin-film devices and new materials for the CMOS roadmap. Solid State Electron 48:961–967
Iwai H (2008) CMOS technology after reaching the scale limit. 8th international workshop on junction technology IWJT, pp 1-2
Jurczak M et al (2009) Review of FINFET technology. IEEE international SOI Conference, pp 1-4
Karel A et al (2016) Comparative study of bulk, FDSOI and FinFET technologies in presence of a resistive short defect. 17th Latin-American test Symposium (LATS’16), Foz do Iguacu, pp 129-134
King T-J (2005) FinFETs for nanoscale CMOS digital integrated circuits. IEEE/ACM international Conference on Computer-aided design (ICCAD’05), pp 207-210
Kruseman B et al (2003) Detection of resistive shorts in deep-submicron technologies. IEEE international test Conference, pp 866-875
Nowak EJ et al (2004) Turning silicon on its edge [double gate CMOS/FinFET technology]. IEEE Circuits and Devices Magazine 20(1):20–31
Philippe M et al (2013) UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency. Design, Automation & Test in Europe Conference & Exhibition (DATE’13), pp 952-957
Planes N et al (2012) 28nm FDSOI technology platform for high-speed low-voltage digital applications. Symposium on VLSI technology (VLSIT’12), pp 133-134
Polian I et al (2005) Resistive bridge fault model evolution from conventional to ultra deep submicron. 23rd IEEE VLSI test Symposium (VTS'05), pp 343-348
Renovell M et al (1995) The concept of resistance interval: a new parametric model for realistic resistive bridging fault. IEEE VLSI test Symposium (VTS'95), pp 184-189
Sinha S et al (2012) Exploring sub-20nm FinFET design with predictive technology models. Annual design Automation Conference (DAC '12). ACM, New York
Skotnicki T et al (2005) New materials and device architectures for the end-of-roadmap CMOS nodes. Mater Sci Eng B 124–125:3–7
Takayasu S et al (2006) Fully-depleted SOI CMOS circuits and technology for ultra-low power aaplication. Springer
Tayade R et al (2007) Small-delay defect detection in the presence of process variations. 8th international Symposium on quality electronic design (ISQED'07). San Jose, pp 711-716
Villacorta H et al (2012) Resistive bridge defect detection enhancement under parameter variations combining low VDD and body bias in a delay based test. In Microelectronics Reliability 52(11):2799–2804
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This work was supported by the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) and University of Montpellier for PhD Graduates.
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Karel, A., Comte, M., Galliere, JM. et al. Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J Electron Test 33, 515–527 (2017). https://doi.org/10.1007/s10836-017-5674-9
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DOI: https://doi.org/10.1007/s10836-017-5674-9