Abstract
It is known that certain faults associated with the process might be generated in any phases of the fabrication and assembly of the complex interconnection structure in a high-speed PCB composed of via holes, solder joints and traces, which will inevitably discount the electrical performance of the circuit. To address the issue, a fault-voltage detection method is proposed in this paper, firstly the equivalent fault circuit of the complex interconnection structure in high-speed PCB is scanned to extract the fault voltage, then the optimal function curve can be fitted out by the least squares method based on the faultless voltage. The empirical research on the via hole crack and solder joint void have validated that this method can effectively avoid the false tests derived under the low-frequency, major-fault and high-frequency, minor-fault conditions, and can also depict more accurately how the fault parameter varies with the changes in the frequency and fault degree, and it bears a relatively strong applicability in minor-fault of hiht-speed PCB tests.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Bogatin E (2005) Signal integrity analysis (trans: Yushan Li, Liping Li) Electronic Industry Press, Beijing
Casares-Miranda FP, Viereck C, Camacho-Penalosa C (2006) Vertical microstrip transition for multilayer microwave circuits with decoupled passive and active layers. IEEE Microwave Wireless Compon Lett 42(1):28–39
Chun S, Kim Y, Kang S (2007) MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. J Electron Test 23(4):357–362
Cracraft M, Connor S, Archambeault B (2014) Unintended Effects of Asymmetric Return Vias and Via Array Design for Reduced Mode Conversion. Proc. IEEE International Symposium on Electromagnetic Compatibility, Raleigh, pp 83–95
Cuviello M, Dey S, Bai XL, Zhao Y (1999) Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects. Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, pp 297–303
Fei Y (2010) Error Theory and Data Processing. Mechanical Industry Press, Beijing
Jiang L, Wu X, Pan Y, Zhang J (2011) An Equivalent Impedance Model for Lead-Free Solder Joints Based on Crack Propagation. Electronic Components and Materials, pp 33–38
Lou Y, Yan Z, Zhang F (2012) Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods. J Electron Test 28(1):27–38
Shang Yuling (2009) High speed interconnect Crosstalk type fault test research. Dissertation, Xi Dian University, pp 63–69
Shang YL, Qu L (2013) Analysis for Modeling Electromagnetic Characteristics of Via in High-Speed Printed Circuit Board. Adv Inf Sci Serv Sci 5(7):589–596
Shang T, Xie L, Ruxu D (2011) MATLAB engineering calculation and analysis. Tsinghua University press, Beijing
Kannan S, Kim B, Ahn B (2012) Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects. Journal of Electronic Testing: Theory and Applications 28(1):39–51
Tehranipour MH, Ahmed N, Nourani M (2003) Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. Proc. 21st International Conference on Computer Design, San Jose, pp 554–559
Wu BP, Tsang L (2010) Signal integrity analysis of package and printed circuit board with multiple vias in substrate of layered dielectrics. IEEE Trans Adv Packag 12(6):123–129
Xiang G, Sheach K, Brunet P (2009) A Study on High-density High-speed SerDes Design in Buildup Flip Chip Ball Grid Array Packages. Proc. European Microelectronics and Packaging Conference, Rimini, pp 248–251
Zhang J (2007) Research on hierarchical test method of SOC. Dissertation, Huazhong University of Science and Technology, pp 23–27
Acknowledgments
The research work reported in this paper is supported by the National Natural Science Foundation of China (Nos.51465013,61661013), Innovation Project of GUET Graduate Education (Nos.GDYCSZ201443, GDYCSZ201480, 2016YJCX104), Guangxi Key Laboratory of Automation Test and Instrumentation (No.YQ15109) and Graduate Research Project of Education Department of Guangxi (YB2014138).
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: E. Amyeen
Rights and permissions
About this article
Cite this article
Shang, Y., Sun, L., Li, C. et al. Test of Mechanical Failure for Via Holes and Solder Joints of Complex Interconnect Structure. J Electron Test 33, 491–499 (2017). https://doi.org/10.1007/s10836-017-5675-8
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-017-5675-8