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A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

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Abstract

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.

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Authors and Affiliations

  1. NXP Semiconductor India Pvt Ltd, Noida, India

    Ankush Srivastava

  2. Indian Institute of Technology Bombay, Mumbai, India

    Ankush Srivastava & Virendra Singh

  3. Auburn University, Auburn, AL, 36849, USA

    Adit D. Singh

  4. University of Wisconsin, Madison, WI, 53706, USA

    Kewal K. Saluja

Authors
  1. Ankush Srivastava
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  2. Virendra Singh
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  3. Adit D. Singh
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  4. Kewal K. Saluja
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Correspondence to Ankush Srivastava.

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Responsible Editor: L. M. Bolzani Pöhls

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Srivastava, A., Singh, V., Singh, A.D. et al. A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J Electron Test 33, 721–739 (2017). https://doi.org/10.1007/s10836-017-5692-7

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  • DOI: https://doi.org/10.1007/s10836-017-5692-7

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