Abstract
In this paper, a 65 nm MOSFET 3D structure is built based on Technology Computer Aided Design (TCAD) 3D device simulation software, and the single-event transient (SET) effect in 65 nm CMOS inverter is analyzed using TCAD-HSPICE mixed-mode simulation based on heavy ion model. The formation and function of the PN junction diffusion capacitance in the Metal-Oxide-Semiconductor (MOS) device are discussed by analyzing the drain and substrate voltage characteristics of the device under the SET effect. Then the sub-circuit structure of this device for SET is established, and the mechanism of the diffusion capacitance of PN junction during the heavy ion action process is verified comparing with the results of sub-circuit HSPICE simulation results and the TCAD-HSPICE simulation results. Finally, A sub-circuit model is provided, to support circuit-level simulation of single-event effects.
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This research was partially supported by Equipment Pre-research Project of China.
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Responsible Editor: V. D. Agrawal
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Yi, T., Liu, Y. & Yang, Y. A Study of PN Junction Diffusion Capacitance of MOSFET in Presence of Single Event Transient. J Electron Test 33, 769–773 (2017). https://doi.org/10.1007/s10836-017-5694-5
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DOI: https://doi.org/10.1007/s10836-017-5694-5