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Gate Oxide Short Defect Model in FinFETs

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Abstract

FinFET technology is one of the most promising candidates in replacing planar MOSFET beyond the 22 nm technology node. However, the complexity of FinFET manufacturing process has caused challenges in reliable device testing. Gate oxide short (GOS) is one of the dominant defects that has significant impact on circuit reliability. In this paper, we present a GOS defect model for FinFETs by introducing the defect as a pinhole in the gate oxide of a triangular fin shape structure. The pinholes are represented by small cuboid cuts of various sizes on the fin top and sidewalls along the channel. The 3D Sentaurus TCAD simulation results in the development of an analytical GOS defect model that can be used in circuit-level fault modeling, which leads to generating more realistic test patterns.

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Acknowledgments

The authors would like to express their appreciation to Dr. Saman Adham for his valuable contribution and to CMC Microsystems and Synopsys Inc. for their support throughout this research.

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Authors and Affiliations

  1. Department of Electronics, Carleton University, Ottawa, Ontario, Canada

    Roya Dibaj & Maitham Shams

  2. Department of Electrical & Computer Engineering, Royal Military College, Kingston, Ontario, Canada

    Dhamin Al-Khalili

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  1. Roya Dibaj
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  2. Dhamin Al-Khalili
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  3. Maitham Shams
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Correspondence to Roya Dibaj.

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Responsible Editor: M. Barragan and K. Huang

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Dibaj, R., Al-Khalili, D. & Shams, M. Gate Oxide Short Defect Model in FinFETs. J Electron Test 34, 351–362 (2018). https://doi.org/10.1007/s10836-018-5727-8

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  • DOI: https://doi.org/10.1007/s10836-018-5727-8

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