Skip to main content
SpringerLink
Log in

High Performance Modified Static Segment Approximate Multiplier based on Significance Probability

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Achieving high accuracy has become a key design objective in high quantity digital data computing devices. To enhance the accuracy, a high performance Modified Static Segment approximate Multiplier (MSSM) is proposed in this paper. It increases the accuracy based on the negating lower order significant information of input operands using Significance Estimator Logic Circuit (SELC). The performance of proposed MSSM is compared with the existing approximate multipliers such as a Dynamic Segment approximate Multiplier (DSM) and Static Segment approximate Multiplier (SSM) for all input combinations. These multipliers are implemented and simulated using Xilinx 14.2 ISE. In MSSM method, 99% of average computational accuracy can be achieved for a 16-bit multiplication even with an 8 × 8-bit multiplier from all combinations of input operands instead of 95% of average computational accuracy from 61% of input operand pair in the existing SSM method. The proposed 16-bit MSSM offers a savings of 83.45% LUTs, 38.78% power and it exhibits 24.40% less delay, 0.6% less computational accuracy than the existing DSM.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. Botella G, García C, Meyer-Bäse U (2013) Hardware implementation of machine vision systems: image and video processing. EURASIP J Adv Sig Pr 152:1–4

    Google Scholar 

  2. Chang CH, Satzoda RK (2010) A low error and high performance multiplexer-based truncated multiplier. IEEE T VLSI Syst 18:1767–1771

    Article  Google Scholar 

  3. Chippa VK, Mohapatra D, Raghunathan A, Roy K, and Chakradhar ST (2010) “Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency,” in Proc. ACM IEEE D, pp. 555–560

  4. Ganesh Kumar KS, Deva Prasannam J, Anitha Christy M (2014) Analysis of low power, area and high performance multipliers for DSP applications. Int J Emerg Technol Adv Eng 4:278–382

    Google Scholar 

  5. Hegde R, Shanbhag NR (1999) "Energy-efficient signal processing via algorithmic noise-tolerance," In: Proceedings international symposium low power electronics and design (ISPLED), pp. 30–35

  6. Iyshwerya K, Janani SK and Manikandan T (2013) “Defect detection algorithm for high speed inspection in machine vision”, Proc Int Conf on Smart Structures & Systems, pp. 103–107

  7. Kishore Kumar A, Somasundareswari D, Duraisamy V, Shunbaga Pradeepa T (2013) Design of low Power Multiplier with energy efficient full adder using DPTAAL. VLSI Des 2013:1–9

    Article  MathSciNet  Google Scholar 

  8. Ko H-J, Hsiao S-F (2011) Design and application of faithfully rounded and truncated multipliers with combined deletion, reduction, truncation, and rounding. IEEE Trans Circuits Syst - II 58(5):304–309

    Article  Google Scholar 

  9. Kulkarni P, Gupta P and Ercegovac M (2011) “Trading accuracy for power with an under designed multiplier architecture,” in Proc 24th IEEE Int Conf VLSI Des, pp. 346–351

  10. Kumar A (2008) Computer vision-based fabric defect detection: a survey. IEEE T Ind Electron 55:348–363

    Article  Google Scholar 

  11. Kumar A, Pang G (2002) Defect detection in textured materials using Gabor filters. IEEE T Ind Appl 38:425–440

    Article  Google Scholar 

  12. Narayanamoorthy S, Moghaddam HA, Liu Z, Park T, Kim NS (2015) Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Trans Very Large Scale Integr (VLSI) Syst 23:1180–1184

    Article  Google Scholar 

  13. Sindia S, Agrawal VD (Aug 2013) Neural network guided spatial fault resilience in Array processors. JETTA 29(4):473–483

    Google Scholar 

  14. Vasudevan M, Chakrabarti C (2014) Image processing using approximate Datapath units. Proc IEEE Int Symp Circuits Sys:1544–1547

  15. Venkatachalam S, Ko S-B (2017) Design of Power and Area Efficient Approximate Multipliers. IEEE Trans Large Scale Integration (VLSI) Syst 25(5):1782–1786

    Article  Google Scholar 

  16. Yuan Q, Huang Y, Yu J (2008) A novel approach for designing interpolation filter using basis functions. Congress Image Signal Proces 5:219–222

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, KGiSL Institute of Technology, Coimbatore, India

    R. Jothin

  2. Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, India

    C. Vasanthanayaki

Authors
  1. R. Jothin
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. C. Vasanthanayaki
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to R. Jothin.

Additional information

Responsible Editor: S. Sindia

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Jothin, R., Vasanthanayaki, C. High Performance Modified Static Segment Approximate Multiplier based on Significance Probability. J Electron Test 34, 607–614 (2018). https://doi.org/10.1007/s10836-018-5748-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-018-5748-3

Keywords

Search

Navigation