Skip to main content
SpringerLink
Log in

A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low design cost and short time-to-market. Besides their vulnerability to hardware Trojan attacks, SRAM-based reconfigurable devices are also significantly susceptible to faults originated by particle strikes. There have been various methods to mitigate either hardware Trojan attacks or faults. To our knowledge, however, no method has been presented that can integrate detecting, distinguishing, and mitigating faults and Trojans. In this paper, we present an efficient method for SRAM-based reconfigurable devices, which is able to perform Trojan detection while detecting and correcting both permanent faults (faults in SRAM configuration bits) and transient faults (faults which affect flip flops, logical elements, and wires) using a single controller circuitry. The efficiency of the proposed method is evaluated with a well-known benchmark implemented on commercial FPGAs. The results show that the availability and reliability of the proposed method are superior to the conventional triple modular redundancy method by more than 100%. The experiments also show that the proposed method improves the average area and area×delay overheads by 32% and 6%, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

References

  1. ABC: A System for Sequential Synthesis and Verification. [Online]. Available : https://people.eecs.berkeley.edu/alanmi/abc

  2. Abramovici M, Bradley P (2009) Integrated circuit security new threats and solutions. In: Proc of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies, New York, pp 1–3

  3. Agrawal D, Baktir S, Karakoyunlu D, Rohatgi P, Sunar B (2007) Trojan detection using IC fingerprinting. In: Proc of the symposium on security and privacy, Berkeley, pp 296–310

  4. Al-Anwar A, Alkabani Y, El-Kharashi MW, Bedour H (2013) Hardware trojan detection methodology for FPGA. In: Proc of the Conference on Communications, Computers and Signal Processing (PACRIM), Victoria, pp 177–182

  5. Al-Anwar A, Alkabani Y, El-Kharashi MW, Bedour H (2013) Hardware trojan protection for third party IPs. In: Proc of the Conference on Digital System Design (DSD), Los Alamitos, pp 662–665

  6. Asadi H, Tahoori MB (2007) Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs. IEEE Transactions on Very Large Scale Integration Systems (VLSI) 15(12):1320–1331

    Article  Google Scholar 

  7. Asadi H, Tahoori MB, Mullins B, Kaeli D, Granlund K (2007) Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems. IEEE Trans Nucl Sci (TNS) 54(6):2714–2726

    Article  Google Scholar 

  8. Æinlar E. (1969) Markov renewal theory, vol 1

  9. Beaumont M, Hopkins B, Newby T (March 2012) SAFER PATH security architecture using fragmented execution and replication for protection against trojaned hardware. In: Proc of the conference on design, automation and test in europe (DATE), San Jose, pp 1000–1005

  10. Berkeley Logic Interchange Format (BLIF). (1993). [Online]. Available: https://www.ece.cmu.edu/ee760/760docs/blif.pdf

  11. Brglez F, Bryan D, Kozminski K (1989) Combinational profiles of sequential benchmark circuits. In: Proc of the symposium on circuits and systems, Portland, pp 1929–1934

  12. Chakraborty RS, Paul S, Bhunia S (2008) On-demand transparency for improving hardware trojan detectability. In: Proc of the Symposium on Hardware-Oriented Security and Trust (HOST), Anaheim, pp 48–50

  13. Cha B, Gupta SK (2013) Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost. In: Proc of Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, pp 1265–1270

  14. Chakraborty RS, Saha I, Palchaudhuri A, Naik GK (2013) Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. IEEE Des Test 30(2):45–54

    Article  Google Scholar 

  15. Cui X, Ma K, Shi L, Wu K (2014) High-Level synthesis for run-time hardware trojan detection and recovery. In: Proc of the 51st Annual Design Automation Conference, New York, pp 1–6

  16. Dutt S, Li L (2009) Trust-Based Design and check of FPGA circuits using Two-Level randomized ECC structures. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 2(1):6:1–6:36

    Google Scholar 

  17. Dynkin EB (1965) Markov processes. In: Markov Processes, Springer, Berlin, pp 77–104

  18. Forte D, Bao C, Srivastava A (2013) Temperature tracking- an innovative Run-Time approach for hardware trojan detection. In: Proc of the international conference on Computer-Aided (ICCAD), piscataway, pp 532–539

  19. Ghaderi Z, Miremadi SG, Asadi H, Fazeli M (2013) HAFTA- highly available fault-tolerant architecture to protect SRAM-based reconfigurable devices against multiple bit upsets. IEEE Trans Device Mater Reliab 13(1):203–212

    Article  Google Scholar 

  20. Govindan V, Chakraborty RS (2018) Logic testing for hardware trojan detection. In: The Hardware Trojan War, Springer, Cham, pp 149–182

  21. Gunti NB, Khatri A, Lingasubramanian K (2014) Realizing a security aware triple modular redundancy scheme for robust integrated circuits. In: Proc of the Conference on Very Large Scale Integration (VLSI-soc), Playa del Carmen, pp 1–6

  22. Jim P, Saqib F (2018) Detecting hardware trojans using delay analysis, In: The Hardware Trojan War, Springer, Cham, pp 219–267

  23. Jin Y, Makris Y (2008) Hardware trojan detection using path delay fingerprint. In: Proc of the symposium on Hardware-Oriented security and trust (HOST), Anaheim, pp 51–57

  24. Khaleghi B, Ahari A, Asadi H, Sarmadi B (2015) FPGA-Based protection scheme against hardware trojan horse insertion using dummy logic. IEEE Journal of Embedded Systems Letters 7(2):46–50

    Article  Google Scholar 

  25. Kitsos P, Voyiatzis AG (2014) FPGA trojan detection using Length-Optimized ring oscillators. In: Proc of the conference on digital system design (DSD), Verona, pp 675–678

  26. Kuon I, Tessier R, Rose J (2008) FPGA Architecture: survey and challenges. Journal of Foundations and Trends in Electronic Design Automation 2(2):135–253

    Article  Google Scholar 

  27. Li J, Lach J (2008) At-Speed delay characterization for IC authentication and trojan horse detection. In: Proc of the symposium on Hardware-Oriented security and trust (HOST), Anaheim, pp 8–14

  28. Mal-Sarkar S, Karam R, Narasimhan S, Ghosh A, Krishna A, Bhunia S (2016) Design and validation for FPGA trust under hardware trojan attacks. IEEE Transactions on Multi-Scale Computing Systems 2(3):186–198

    Article  Google Scholar 

  29. Mal-Sarkar S, Krishna A, Ghosh A, Bhunia S (2014) Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures. In: Proc of the 24th Edition of the Great Lakes Symposium on VLSI (GLSVLSI), New York, pp 287–292

  30. Mao S, Liu L (2016) OPTMR: Optimal data flow graph partitioning for triple modular redundancy against hardware Trojan in reconfigurable hardware. In: Proc of the 6th IEEE International Conference on Electronics Information and Emergency Communication (ICEIEC), pp 68–71

  31. McIntyre D, Wolff F, Papachristou C, Bhunia S, Weyer D (2009) Dynamic evaluation of hardware trust. In: Proc of the Symposium on Hardware-Oriented Security and Trust (HOST), Francisco, pp 108–111

  32. McIntyre D, Wolff F, Papachristou C, Bhunia S (2010) Trustworthy computing in a multi-core system using distributed scheduling. In Proc of the International On-Line Testing Symposium (IOLTS), Corfu, pp 211–213

  33. Mooney, Christopher Z (1997) Monte Carlo simulation. Sage publications

  34. Newgard B, Hoffman C (2010) Using multiple processors in a single reconfigurable fabric for High-Assurance applications. In: Proc of the symposium on Hardware-Oriented security and trust (HOST), Anaheim, pp 25–29

  35. Open Circuit Design. [Online]. Available: http://opencircuitdesign.com

  36. Rajendran J, Zhang H, Sinanoglu O, Karri R (2013) High-Level synthesis for security and trust. In: Proc of the international On-Line testing symposium (IOLTS), Chania, pp 232–233

  37. Rilling J, Graziano D, Hitchcock J, Meyer T, Wang X, Jones P, Zambreno J (2011) Circumventing a ring oscillator approach to FPGA-based hardware trojan detection. In: Proc of the International Conference on Computer Design (ICCD), Amherst, pp 289–292

  38. Roy JA, Koushanfar F, Markov IL (2008) EPIC: Ending piracy of integrated circuits. In: Proc. of the Conference on Design, Automation and Test in Europe (DATE), Munich, pp 1069–1074

  39. Salmani H, Tehranipoor M, Plusquellic J (2012) A novel technique for improving hardware trojan detection and reducing trojan activation time. IEEE Trans Very Large Scale Integr VLSI Syst 20(1):112–125

    Article  Google Scholar 

  40. Santangelo L (2014) Viv2XDL: a bridge between Vivado and XDL based software, Master’s Thesis, University of Pisa. [Online]. Available : https://etd.adm.unipi.it/t/etd-09012014-224107 https://etd.adm.unipi.it/t/etd-09012014-224107

  41. Senwen K, Ottavi M, Dworak J (2015) Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Proc of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp 119–122

  42. Wang X, Tehranipoor M, Plusquellic J (2008) Detecting malicious inclusions in secure hardware: challenges and solutions. In: Proc of the symposium on Hardware-Oriented security and trust (HOST), Anaheim, pp 15–19

  43. Wang X, Salmani H, Tehranipoor M, Plusquellic J (2008) Hardware trojan detection and isolation using current integration and localized current analysis. In: Proc of the symposium on defect and fault tolerance of VLSI systems (DFTVS), Boston, pp 87–95

  44. Wolff F, Papachristou C, Bhunia S, Chakraborty RS (2008) Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. In: Proc of the Conference on Design, Automation and Test in Europe (DATE), New York, pp 1362–1365

  45. Wu Tony F, et al (2016) Tpad: Hardware Trojan prevention and detection for trusted integrated circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 35.4:521–534

    Article  Google Scholar 

  46. Xilinx Inc. [Online]. Available : http://www.xilinx.com

  47. Zhang X, Tehranipoor M (2011) RON- an on-chip ring oscillator network for hardware trojan detection. In: Proc of the Conference on Design, Automation and Test in Europe (DATE), Grenoble, pp 1–6

Download references

Author information

Authors and Affiliations

  1. Department of Computer Engineering, Sharif University of Technology, Tehran, Iran

    Omid Ranjbar, Siavash Bayat-Sarmadi, Fatemeh Pooyan & Hossein Asadi

Authors
  1. Omid Ranjbar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Siavash Bayat-Sarmadi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Fatemeh Pooyan
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Hossein Asadi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Siavash Bayat-Sarmadi.

Additional information

Responsible Editor: S. Bhunia

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ranjbar, O., Bayat-Sarmadi, S., Pooyan, F. et al. A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. J Electron Test 35, 201–214 (2019). https://doi.org/10.1007/s10836-019-05783-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-019-05783-2

Keywords

Search

Navigation