Skip to main content
Log in

Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

In this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on each deskew buffer within the microprocessor can be significantly different, depending on how each deskew buffer is configured after fabrication (to compensate clock skews occurring during the fabrication process) and the operating temperature. Therefore, we show that even if deskew buffers compensate skews among clock signals after fabrication, their different level of degradation during circuit lifetime can generate significant skews between clock signals after only some month of circuit operation in the field. Moreover, the variations in the delay of deskew buffers due to BTI can exceed the maximum compensation range enabled by such schemes, thus making skew compensation during circuit lifetime ineffective. Finally, we propose a simple mathematical model enabling to estimate the maximum skew among clock signals during the chip lifetime. The model can be used to activate proactive compensation approaches (e.g., clock frequency reduction) allowing to avoid malfunctions caused by an excessive skew among clock signals generated by BTI degradation of the deskew buffers.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4

Similar content being viewed by others

References

  1. Alam MA, Mahapatra S (2005) A comprehensive model of PMOS NBTI degradation. Microelectron Reliab 45:71–81

    Article  Google Scholar 

  2. F. Caignet, D. Delmas-Bendhia, E. Sicard, (2001) The Challenge of Signal Integrity in Deep Submicrometer CMOS Technology, in Proc. of IEEE, pp. 556–573

  3. T.-L. Chu, W.-Y. Chu, Y. Fujii, C.-S. Hwang, (2015) All-digital deskew buffer using a hybrid control scheme, in Proc. of IEEE International System-on-Chip Conference (SOCC), pp. 30–34

  4. Chung CC, Hou CY (2017) An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. Microelectron J 70:63–71

    Article  Google Scholar 

  5. Dehng GK, Hsu JM, Yang CY, Liu SI (2000) Clock-deskew buffer using a SAR-controlled delay-locked loop. IEEE J Solid State Circuits 35(8):1128–1136

    Article  Google Scholar 

  6. C. E. Dike, N. A. Kurd, P. Patra, J. Barkatullah, (2003) A Design for Digital, Dynamic Clock Deskew, in Symp. VLSI Circuits Dig. Tech. Papers, pp. 21–24

  7. V. Huard, M. Denais, (2004) Hole Trapping Effect on Methodology for DC and AC Negative Bias Temperature Instability Measurements in PMOS Transistors, in Proc. of IEEE Int. Rel. Physics Symp., pp 40–45

  8. K. Joshi, S. Mukhopadhyay, N. Goel, S. Mahapatra, (2012) A consistent physical framework for N and P BTI in HKMG MOSFETs, in Proc. of IEEE Int. Reliability Physics Symposium (IRPS), vol., no., pp.5A.3.1-5A.3.10, 15–19

  9. J. Keane, T-H. Kim, C. H. Kim, (2009) An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation, IEEE Trans. On Very Large Scale Integration (VLSI) Syst.

  10. Kukner H, Khan S, Weckx P, Raghavan P, Hamdioui S, Kaczer B, Catthoor F, Van der Perre L, Lauwereins R, Groeseneken G (2014) Comparison of reaction-diffused and atomistic trap-based BI models for logic gates. IEEE Trans Device Mater Reliab 14(1):182–193

    Article  Google Scholar 

  11. Kurd NA, Barkatullah JS, Dizon RO, Fletcher TD, Madland PD (2001) A multigigahertz clocking scheme for the Pentium 4 microprocessor. IEEE J Solid State Circuits 36(11):1647–1653

    Article  Google Scholar 

  12. Y. Lee, S.H. Huang, (2017) On-chip-variation-aware power-mode-aware buffer synthesis for clock skew minimization, In: International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1–2

  13. K.T. Lee, W. Kang, E.A. Chung, G. Kim, H. Shim, H. Lee, H. Kim, M. Choe, N.I. Lee, A. Patel, J. Park, J. Park, (2013) Technology scaling on High-K & metal-gate FinFET BTI reliability, IEEE International Reliability Physics Symposium (IRPS), pp. 2D.1.1-2D.1.4

  14. M. Omaña, D. Rossi, C. Metra, (2004) Fast and Low-Cost Deskew Buffer, in Proc. of IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 202–210

  15. M. Omaña, D. Rossi, C. Metra, (2005) Low Cost Scheme for On-Line Clock Skew Compensation, in Proc. of IEEE VLSI Test Symposium, pp. 90–95

  16. M. Omaña, D. Rossi, N. Bosio, C. Metra, (2010) Novel Low-Cost Aging Sensor, in Proc. of ACM Computing Frontiers Conference, pp. 93–94

  17. J.-H. Park, D.-H. Jung, K. Ryu, S.-O. Jung, (2013) ADDLL for Clock-Deskew Buffer in High-Performance SoCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.: 21, Issue: 7, pp. 1368–1373

  18. L. Puneeth, N. Murty (2015) Low power clock Optimized Digital De-Skew Buffer with improved duty cycle correction, in Proc. of IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), pp. 1–5

  19. Rossi D, Cazeaux JM, Omaña M, Metra C, Chatterjee A (2009) Accurate linear model for SET critical charge estimation. IEEE Trans VLSI Syst 17(8):1161–1166

    Article  Google Scholar 

  20. J. Segura, C. F. Hawkins, (2004) How it works, how it fails, John Wiley & Son, Inc.

  21. M. Toledano-Luque, B. Kaczer, J. Franco, Ph. J. Roussel, T. Grasser, T. Y. Hoffmann, G. Groeseneken, (2011) From Mean Values to Distribution of BTI Lifetime of Deeply Scaled FETs Through Atomistic Understanding of the Degradation, in Symposium on VLSI Technology, Digest of Technical Papers, pp. 152–153

  22. Tu YH, Liu JC, Cheng KH, Hsu CH (2017) A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs. Analog Integr Circ Sig Process 93(1):157–167

    Article  Google Scholar 

  23. Velamala JB, Sutaria KB, Shimizu H, Awano H, Sato T, Wirth G, Cao Y (2013) Compact modeling of statistical BTI under trapping/detrapping. IEEE Trans Electron Devices 60(11):3645–3654

    Article  Google Scholar 

  24. W. Wang, Z. Wei, S. Yang, Y. Cao, (2007) An Efficient Method to Identify Critical Gates under Circuit Aging, in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 735–740

  25. Weste N, Harris D (2004) CMOS VLSI design a circuits and systems perspective. Addison-Wesley, New York

    Google Scholar 

  26. Yang H-I, Hwang W, Chuang C-T (2011) Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high- \kappa metal-gate devices. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(7):1192–1204

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Marco Grossi.

Additional information

Responsible Editor: V. Champac

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Grossi, M., Omaña, M. Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers. J Electron Test 35, 261–267 (2019). https://doi.org/10.1007/s10836-019-05788-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-019-05788-x

Keywords

Navigation