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Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique

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Abstract

This paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bit modified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended to implement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based on metrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it is observed that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventional adders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% power reduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGA Spartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventional design.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Coimbatore, Institute of Technology, Coimbatore, India

    S. Geetha & P. Amritvalli

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  1. S. Geetha
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  2. P. Amritvalli
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Correspondence to S. Geetha.

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Responsible Editor: S. Sindia

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Geetha, S., Amritvalli, P. Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique. J Electron Test 35, 383–400 (2019). https://doi.org/10.1007/s10836-019-05802-2

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