Abstract
System in package (SiP) has become a major trend for state-of-the-art devices in semiconductor industry. The decreasing dimension of its redistribution layers (RDLs) makes defective connection more prone to occur but harder to detect. This study proposes new metrology ideas verified experimentally to guarantee the SiP RDL connectivity. The major challenges are testability of <500 Ω open on a trace and especially highly resistive paths between RDL traces that can develop into serious short-circuits over time. Inspection of the RDLs after packaging cannot use the same techniques as used in probing bare printed circuit boards due to the danger of damaging embedded parts. This manuscript provides solutions that can guarantee the same level of quality assurance in the open and the short inspection as conventional test methods can. These techniques enable accurate probing of as small as 50 Ω for open defects and up to 100 MΩ for short defects using only 0.2 V, which is ~1000 times smaller signal than what is used in the conventional high-voltage technique.
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Kang, J., Chae, K. & Jeong, J. Connectivity Test for System in Package Interconnects. J Electron Test 35, 559–565 (2019). https://doi.org/10.1007/s10836-019-05810-2
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DOI: https://doi.org/10.1007/s10836-019-05810-2