Skip to main content
SpringerLink
Log in

Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Power analysis attack is a form of side channel attack which can recover the key of a cryptographic algorithm running on some device. In this work we propose CAD based methodology to perform power analysis on pre-silicon gate-level netlist of cryptographic algorithm. We first build a new leakage model of the critical component present in crypto design by approximating it’s dynamic power consumption from the toggle count information. Then using the power model we perform power attack to recover key using power trace of crypto design. We validated our methodology on PRESENT like cipher structure and also compared our leakage model with popular Hamming distance and Hamming weight models, where we found our model requires very less number of power traces to recover keys with high correlation. We further extended our model to work by counting the number of toggles, that can be exploited by the circuit designers to early detect if their crypto design is vulnerable to any leakage or by tool developers to induct security awareness in their flow. Finally, we integrated our methodology with hybrid testing framework for first order side channel analysis to certify crypto-implementations from pre-silicon power analysis.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Akkar ML, Bevan R, Dischamp P, Moyart D (2000). In: Okamoto T (ed) Proc. advances in cryptology — ASIACRYPT 2000. Springer, Berlin, pp 489–502

  2. Bayrak AG, Regazzoni F, Brisk P, Standaert F, Ienne P (2011). In: Proceedings of the 48th design automation conference, DAC 2011, San Diego, California, USA, June 5–10, 2011, pp 230–235, DOI https://doi.org/10.1145/2024724.2024778, (to appear in print)

  3. Brier E, Clavier C, Olivier F (2004). In: Joye M, Quisquater JJ (eds) Proc. cryptographic hardware and embedded systems - CHES 2004. Springer, Berlin, pp 16–29

  4. Chandrakasan AP, Brodersen RW (eds.) (1997) Low-power CMOS design, 1st edn. Wiley-IEEE Press

  5. Goodwill G, Jun B, Jaffe J, Rohatgi P (2011)

  6. He MT, Park J, Nahiyan A, Vassilev A, Jin Y, Tehranipoor M (2019). In: Proc. 37th IEEE VLSI test symposium, VTS 2019, Monterey, CA, USA, April 23–25, 2019, pp 1–6, DOI https://doi.org/10.1109/VTS.2019.8758600, (to appear in print)

  7. Huss SA, Stöttinger M, Zohner M (2013). In: AMASIVE: an adaptable and modular autonomous side-channel vulnerability evaluation framework. Springer, Berlin, pp 151–165, DOI https://doi.org/10.1007/978-3-642-42001-6_12, (to appear in print)

    Google Scholar 

  8. Knudsen LR, Leander G. (2011) PRESENT– block cipher. Springer, Boston, pp 953–955

    Book  Google Scholar 

  9. Kocher P, Jaffe J, Jun B (1999). In: Wiener M (ed) Proc. advances in cryptology — CRYPTO’ 99. Springer, Berlin, pp 388–397

  10. Liu H, Qian G, Goto S, Tsunoo Y (2011). In: Chung Y, Yung M (eds) Proc. Information security applications. Springer, Berlin, pp 191–205

  11. Mangard S, Pramstaller N, Oswald E (2005). In: Rao JR, Sunar B (eds) Proc. Cryptographic hardware and embedded systems – CHES 2005. Springer, Berlin, pp 157–171

  12. Peeters E, Standaert FX, Quisquater JJ (2007) . Integr VLSI J 40(1):52. https://doi.org/10.1016/j.vlsi.2005.12.013

    Article  Google Scholar 

  13. Roy DB, Bhasin S, Guilley S, Heuser A, Patranabis S, Mukhopadhyay D (2019) . IEEE Trans Comput 68(3):347. https://doi.org/10.1109/TC.2018.2875746

    Article  MathSciNet  Google Scholar 

  14. Sadhukhan R, Datta N, Mukhopadhyay D (2019). In: Proc. 32nd International conference on VLSI design and 2019 18th international conference on embedded systems, VLSID 2019, Delhi, India, January 5–9, 2019, pp 531–532, DOI https://doi.org/10.1109/VLSID.2019.00121, (to appear in print)

  15. Sadhukhan R, Datta N, Mukhopadhyay D (2019) IEEE Trans Very Large Scale Integr(VLSI) Syst, 1–13. https://doi.org/10.1109/TVLSI.2019.2925421

    Article  Google Scholar 

  16. Sakiyama K, Sasaki Y, Li Y (2015) Security of block ciphers: from algorithm design to hardware implementation, 1st edn. Wiley Publishing

  17. Specification for the advanced encryption standard (aes). Federal Information Processin Standards Publication 197 (2001). http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

  18. Standaert FX, Malkin TG, Yung M (2009). In: Joux A (ed) Proc. advances in cryptology - EUROCRYPT 2009. Springer, Berlin, pp 443–461

  19. Veshchikov N, Guilley S (2017). In: Proc. 2017 IEEE European symposium on security and privacy, EuroS&P 2017, Paris, France, April 26–28, 2017, pp 51–59, DOI https://doi.org/10.1109/EuroSP.2017.31, (to appear in print)

  20. Zhou Y, Feng D (2005) Side-channel attacks: ten years after its publication and the impacts on cryptographic module security testing. http://eprint.iacr.org/2005/388. Zyb@is.iscas.ac.cn 13083 received 27 Oct 2005

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India

    Rajat Sadhukhan, Paulson Mathew, Debapriya Basu Roy & Debdeep Mukhopadhyay

Authors
  1. Rajat Sadhukhan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Paulson Mathew
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Debapriya Basu Roy
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Debdeep Mukhopadhyay
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Rajat Sadhukhan.

Additional information

Responsible Editor: K. Basu

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sadhukhan, R., Mathew, P., Roy, D.B. et al. Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs. J Electron Test 35, 605–619 (2019). https://doi.org/10.1007/s10836-019-05826-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-019-05826-8

Keywords

Search

Navigation