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Leveraging Balanced Logic Gates as Strong PUFs for Securing IoT Against Malicious Attacks

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Abstract

A wave dynamic differential logic (WDDL)-based advanced encryption standard (AES) cryptographic circuit is explored as a strong physical unclonable function (PUF) primitive by exploiting the random load capacitance mismatches in WDDL gates induced by the fabrication process. As compared to the regular CMOS logic gates, the WDDL gates enhance the entropy of the proposed WDDL-based AES strong PUF significantly against power attacks. Furthermore, a non-linear product function is applied into the WDDL-based AES strong PUF to generate a high degree of the non-linearity between the input challenges and the output responses against machine-learning attacks. As demonstrated in results, the proposed WDDL-based AES strong PUF primitive achieves an approximately 50.7% inter-hamming distance (HD) and 97.7% reliability with a less than 25% loss ratio of input power entropy after power attacks and a large linear matching error (1032%) against machine-learning attacks.

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Notes

  1. The number of CRPs can be further increased if a 196-bit AES or 256-bit AES is utilized for building the WDDL-based AES strong PUF.

  2. Vi(t) is the electric potential of the line Wi where t is the timing, as shown in Fig. 2.

  3. Standard simulation means the simulation neglects the variations of process, voltage, and temperature (PVT).

  4. Monte Carlo simulation represents the variations of process are included in the simulation.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA, 23529, USA

    Weize Yu & Yiming Wen

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  1. Weize Yu
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  2. Yiming Wen
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Correspondence to Weize Yu.

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Responsible Editor: T. Xia

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Yu, W., Wen, Y. Leveraging Balanced Logic Gates as Strong PUFs for Securing IoT Against Malicious Attacks. J Electron Test 35, 853–865 (2019). https://doi.org/10.1007/s10836-019-05833-9

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