Abstract
Selecting the ideal trade-off between reliability improvement and cost (i.e., area, timing and power overhead) associated with a fault tolerant architecture generally requires an extensive Design Space Exploration. In this paper, we present a feasibility study that addresses the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Four different selective hardening methods have been investigated and compared: i) a full duplication scheme, ii) a reduced duplication scheme based on a structural susceptibility analysis, iii) a reduced duplication scheme based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication scheme that uses an approximate version of the arithmetic circuit. Experimental results performed on adder and multiplier case studies demonstrate the interest of using approximate structures in a duplication scheme since they provide much better error detection capability than other selective hardening methods with lower area and power overheads. Note that all experiments have been done without considering the area and power overhead due to the comparators. This may slightly biased the results from a quantitative point of view, although it does not jeopardize the main conclusion about the interest of using approximate structures as duplication scheme. Moreover, validations using a gate-level fault injection campaign have shown that approximate structures offer a better reliability level compared to the other considered duplication scenarios.
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References
Al-Maaitah K, Qiqieh I, Soltan A, Yakovlev A (2017) Configurable-accuracy approximate adder design with light-weight fast convergence error recovery circuit. In: Proc. IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT), pp 1–6
Bottoni C, Coeffic B, Daveau J-M, Naviner L, Roche P (2015) Partial Triplication of a Sparc-v8 Microprocessor using Fault Injection. In: Proc. of IEEE Latin American Symposium on Circuits and Systems, pp 1–4
Design Compiler. [Online]. Available: https://www.synopsys.com/
Fazeli M, Ahmadian S, Miremadi S, Asadi H, Tahoori M (2011) Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients. In: Proc. of Design Automation and Test in Europe, pp 1–6
Gomes IAC, Martins M, Reis A, Kastensmidt FL (2015) Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron Reliab 55(9–10):2072–2076
Krstić M, Weidling S, Petrović V, Goessel M (2014) Improved circuitry for soft error correction in combinational logic in pipelined designs. In: Proc. of IEEE 20th International On-Line Testing Symposium, pp 93–98
Leveugle R, Calvez A, Maistri P, Vanhauwaert P (2009) Statistical fault injection: Quantified error and confidence. In: Proc. of IEEE/ACM/EDAA Design Automation and Test in Europe, pp 502–506
Maniatakos M, Makris Y (2010) Workload-Driven Selective Hardening of Control State Elements in Modern Microprocessors. In: Proc. of IEEE VLSI Test Symposium, pp 159–164
Mohanram K, Touba N (2003) Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. In: Proc. of IEEE Int. Test Conference, pp 893–901
Mrazek V, Hrbacek R, Vasicek Z, Sekanina L (2017) Evoapprox8b: Library of Approx Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of IEEE/ACM/EDAA Design Automation and Test in Europe, pp 258–261
NanGate. Nangate 45nm open cell library. [Online]. Available: http://www.nangate.com/?page id=2325
Pagliarini SN et al (2012) Selective Hardening Methodology for Combinational Logic. In: Proc. of IEEE Latin American Test Workshop, pp 1–6
Polian I, Hayes J (2011) Selective hardening: toward cost-effective error tolerance. IEEE Design Test of Computers 28(3):54–63
Polian I, Reddy S, Becker B (2008) Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. In: Proc. of IEEE Annual Symposium on VLSI, pp 257–262
Sanchez-Clemente AJ, Entrena L, Hrbacek R, Sekanina L (2016) Error mitigation using approximate logic circuits : a comparison of probabilistic and evolutionary approaches. IEEE Trans Reliab 65(4):1871–1883
Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A (2018) Testing approximate digital circuits: Challenges and opportunities. In: Proc. of IEEE Latin American Test Symposium, pp 1–6
Wali I, Deveautour B, Virazel A, Bosio A, Dilillo L, Girard P (2015) An Effective Hybrid Fault-Tolerant Architecture for Pipelined Cores. In: Proc. of IEEE European Test Symposium, pp 1–6
Wali I, Virazel A, Bosio A, Girard P, Pravossoudovitch S, Sonza Reorda M (2016) A hybrid fault-tolerant architecture for highly reliable processing cores. Journal of Electronic Testing – Theory and Applications 32(2):147–161
Wali I, Deveautour B, Virazel A, Bosio A, Girard P, Sonza Reorda M (2017) A low-cost reliability vs. cost trade-off methodology to selectively harden logic circuits. Journal of Electronic Testing – Theory and Applications 33(31):25–36
Weidling S, Sogomonyan ES, Goessel M (2013) Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection. In: Proc. of Euromicro Conference on Digital System Design, pp 855–862
Wirth G, Kastensmidt L, Fernanda IR (2008) Single event transients in logic circuits-load and propagation induced pulse broadening. IEEE Trans Nucl Sci 55(6):2928–2935
Zoellin C, Wunderlich H, Polian I, Becker B (2008) Selective Hardening in early Design Steps. In: Proc. of IEEE European Test Symposium, pp 185–190
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This work has been partially funded by the French government under the framework of the PENTA HADES (Hierarchy-Aware and secure embedded test infrastructure for Dependability and performance Enhancement of integrated Systems) European project.
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Deveautour, B., Virazel, A., Girard, P. et al. On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J Electron Test 36, 33–46 (2020). https://doi.org/10.1007/s10836-020-05858-5
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DOI: https://doi.org/10.1007/s10836-020-05858-5