Skip to main content
SpringerLink
Log in

Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The biggest challenge in the verification industry is to create a sufficient number of valid test cases to acquire the desired coverage closure. The design complexity is relentlessly increasing with the number of gates, IPs, embedded processors, software content, and many more. It diverts the research once again to a point, where verification needs a productivity boost to cope with increasing design complexity. The extensive SoC design verification processes are using different execution platforms like simulation, emulation and FPGA prototyping. Each of these platforms requires different ways of specifying tests. The productivity and time demand a single test intent to reuse it across all verification execution platforms. Universal verification methodology (UVM) provides a verification efficiency jump from directed tests to constraint random tests. Synthesis allows the design productivity to jump from gate level to RTL level. Similarly, the SoC verification needs a higher-level of abstraction for automation enactment across all execution platforms. The proposed work derives a test intent on a UVM register abstraction testbench to generate automated test cases. It also assists in the improved functional coverage metric through bug resistant algorithm. The testbench also saves the manual effort of writing test cases. The work improves the simulation time, CPU time, and functional coverage closure in lesser number of transactions as compared to state of the art test benches.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Listing 1
Listing 2
Listing 3
Listing 4
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18

Similar content being viewed by others

References

  1. Santarini M (2005) Asic prototyping: Make versus buy. 50(11):30–40

  2. Bich Ngoc Do T, Kitamura T, Nguyen VT, Hatayama G, Sakuragi S, Ohsaki H (2013) Constructing test cases for n-wise testing from tree-based test models. In: Proceedings of the fourth symposium on information and communication technology, SoICT ’13. ACM, New York, pp 275–284

  3. Fathy K, Salah K. (2016) An efficient scenario based testing methodology using uvm. In : Proceedings of 17th international workshop on microprocessor and soc test and verification (MTV), pp 57–60

  4. Sharma G, Bhargava L, Kumar V (2018) Automated coverage register access technology on uvm framework for advanced verification. In : Proceedings of IEEE international symposium on circuits and systems (ISCAS), pp 1–4

  5. Kirchsteiger CM, Trummer C, Steger C, Weiss R, Pistauer M (2008) Automatic verification plan generation to speed up soc verification. In : Proceedings of IEEE nordic circuits and systems conference (NORCAS) and international symposium of system-on-chip (SoC) (NORCHIP), pp 33–36

  6. Haedicke F, Le HM, Große D, Drechsler R (2012) Crave: an advanced constrained random verification environment for systemc. In : Proceedings of International Symposium on System on Chip (SoC), pp 1–7

  7. Naik K, Sarikaya B (1993) Test case verification by model checking. Form Methods in Syst Des 2(3):277–321

    Article  Google Scholar 

  8. Ara K, Suzuki K (2003) A proposal for transaction-level verification with component wrapper language. In : Proceedings of design, automation and test in europe conference and exhibition, pp 82–87 suppl.

  9. Auri MR, Vincenzi TB, de Oliveira DG, de Souza SRS, Maldonado JC (2016) The complementary aspect of automatically and manually generated test case sets. In: Proceedins of the 7th international workshop on automating test case design, selection, and evaluation, A-TEST 2016. ACM, New York, pp 23–30

  10. Iliuţ I, Ţepuş C (2014) Constraint random stimuli and functional coverage on mixed signal verification. In: Proceedings of international semiconductor conference (CAS), pp 237–240

  11. Ara K, Suzuki K (2005) Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level. IEEE Trans Comput Aided Design Integr Circuits Syst 24(8):1234–1240

    Article  Google Scholar 

  12. Cieplucha M (2019) Metric-driven verification methodology with regression management. J Electron Test 35 (1):101–110

    Article  Google Scholar 

  13. Yurov LV (2015) Quality assessment of verification methodologies and verification procedures. Meas Tech 58 (1):38–45

    Article  Google Scholar 

  14. Wakabayashi K, Okamoto T (2000) C-based soc design flow and eda tools: an asic and system vendor perspective. IEEE Trans Comput Aided Design Integr Circuits Syst 19(12):1507–1522

    Article  Google Scholar 

  15. Elakkiya C, Murty NS, Babu C, Jalan G (2017) Functional coverage - driven uvm based jtag verification. In : Proc of IEEE international conference on computational intelligence and computing research (ICCIC), pp 1–7

  16. Floyd. RW (1993) Assigning Meanings to Programs. Springer, Dordrecht, pp 65–81

  17. El-Ashry S, Salah K (2015) A functional coverage approach for direct testing: an industrial ip as a case study. In : Proc. of IEEE EUROCON 2015 - international conference on computer as a tool (EUROCON), pp 1–6

  18. Marchetto A, Islam MM, Asghar W, Susi A, Scanniello G (2016) A multi-objective technique to prioritize test cases. IEEE Trans Softw Eng 42(10):918–940

    Article  Google Scholar 

  19. Tekcan T, Zlokolica V, Pekovic V, Teslic N, Gunduzalp M (2012) User-driven automatic test-case generation for dtv/stb reliable functional verification. IEEE Trans Consum Electron 58(2):587–595

    Article  Google Scholar 

  20. Plaza SM, Markov IL, Bertacco V (2008) Random stimulus generation using entropy and xor constraints. In : Proceedings of Design Automation and Test in Europe, pp 664–669

  21. Wu B, Yang C, Huang C (2014) A high-throughput and arbitrary-distribution pattern generator for the constrained random verification. IEEE Trans Comput Aided Design Integr Circuits Syst 33(1):139–152

    Article  Google Scholar 

Download references

Acknowledgements

This work is supported by the Ministry of Electronics and Information Technology (Meity), Government of India.

Author information

Authors and Affiliations

  1. MNIT, Jaipur, India

    Gaurav Sharma & Lava Bhargava

  2. NXP Semiconductors, Noida, India

    Vinod Kumar

Authors
  1. Gaurav Sharma
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Lava Bhargava
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Vinod Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Gaurav Sharma.

Additional information

Responsible Editor: N. Nicolici

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sharma, G., Bhargava, L. & Kumar, V. Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification. J Electron Test 36, 219–237 (2020). https://doi.org/10.1007/s10836-020-05866-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-020-05866-5

Keywords

Search

Navigation