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Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation

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Abstract

For the purpose of evaluating the impact of excitation on double data rate (DDR) interface system transmission performance, a methodology for generating the worst-case excitation is proposed for signal integrity (SI) and power integrity (PI) co-simulation. The excitation is produced with the pseudo random bit sequence (PRBS) gated by a square wave of the resonant frequency of the system power distribution network (PDN). The PRBS can reflect non-ideal factors as crosstalk, reflection and loss in the signal line, and the resonant frequency of the PDN can guarantee the maximum simultaneous switching noise (SSN). A data transmission performance simulation environment of currently widely used low power double data rate SDRAM4 (LPDDR4) is constructed based on the advanced I/O buffer information specification Plus (IBIS Plus) model. Compared with the ordinary PRBS excitation, in terms of eye diagrams, the proposed worst-case excitation reduces the eye width and eye height by 4.7% and 19.9%, respectively. Further analysis also proved that 1/2 duty ratio of the gating wave can maximize the influence from the power noise. In conclusion, the proposed worst-case excitation and test environment provide an improved SI/PI co-simulation scenario for the examination of the robustness of DDR system data transmission performance.

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References

  1. Bai Cl, Wang Hs, Guo Y, Yu Qd, Wan C (2019) DDR I/O jitter analysis with IBIS plus model. China Integr Circ 28(Z1):65–68 + 85

    Google Scholar 

  2. Bogatin E (2004) Signal integrity - simplified. Prentice Hall Professional Technical Reference

  3. Cai KX, Ji SY, Dakroub M, Chakraborty R (2016) Signaling margin oriented LPDDR PDN design with SIPI synthesis methodology. In: Proc. IEEE International symposium on electromagnetic compatibility. https://doi.org/10.1109/ISEMC.2016.7571602, pp 50–53

  4. Chan CK, Wu TM, Wu ML, Fan GJ, Shiah C, Lu NC, Wu TL (2018) Signal/power integrity co-simulation of DDR3 memory module. In: Proc. 2018 IEEE International conference on computational electromagnetics (ICCEM). https://doi.org/10.1109/COMPEM.2018.8496538, pp 1–3

  5. Chandrasekhar J, Shim Y (2014) Noise transfer from receiver to transmitter circuits of tranceivers through power supply network(PDN). In: Proc. IEEE International symposium on electromagnetic compatibility. https://doi.org/10.1109/ISEMC.2014.6899021, pp 485–490

  6. Chen SS (2005) Crosstalk analysis in signal integrity. J Wuhan Autom Polytech Univ 27(5):17–19

    Google Scholar 

  7. Cheng W, Sarkar A, Lin S, Zheng J (2009) Worst-case switching pattern for core noise analysis. In: Proc. DesignCon

  8. IBIS (2008) Ibis version 5.0 http://ibis.org/ver5.0, accessed Aug 29 (2008)

  9. Jo J, Kim S, Lee S, Pae S (2016) System-level practical dynamic voltage drop simulation with IC internal VRM. In: Proc. 2016 IEEE 20th workshop on signal and power integrity (SPI). https://doi.org/10.1109/SaPIW.2016.7496264, pp 1–4

  10. Kho J, Loh CI, Krsnik B, Li Z, Fong CS, Boyle P, Wong MO (2008) Effect of SSN-induced PDN noise on a LVDS output buffer. In: Proc. Asia-Pacific conference on IEEE. https://doi.org/10.1109/apace.2007.4603878, pp 1–5

  11. Kim J (2015) Analytical calculation of pattern-dependent simultaneous switching outputs (SSO) due to power supply fluctuations. In: Proc. 2015 IEEE Electrical design of advanced packaging and systems symposium (IEEE EDAPS). https://doi.org/10.1109/EDAPS.2015.7383716, pp 225–228

  12. Liu X, Zhu Z, Yang Y, Wang F, Ding R (2014) Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips. J Semicond 35(1):015008. https://doi.org/10.1088/1674-4926/35/1/015008

    Article  Google Scholar 

  13. Meng H, Niu M, Tan A, Miao J (2018) Power and signal integrity analysis of high-speed mixed-signal backplanes based on VPX. In: Proc. 2018 IEEE symposium on electromagnetic compatibility, signal integrity and power integrity. https://doi.org/10.1109/EMCSI.2018.8495383, pp 577–581

  14. Okubo T, Sudo T, Hosoi T, Tsuyoshi H, Fujio K (2013) Signal transmission loss on printed circuit board in GHz frequency region. In: Proc. 2013 IEEE Electrical design of advanced packaging systems symposium (EDAPS),. https://doi.org/10.1109/EDAPS.2013.6724402, pp 112–115

  15. Pandey AK (2016) Power-aware signal integrity analysis of DDR4 data bus in onboard memory module. In: Proc. 2016 IEEE 20th workshop on signal and power integrity (SPI), pp 1–4, DOI https://doi.org/10.1109/SaPIW.2016.7496261, (to appear in print)

  16. Qian J, Pan S (2014) Power distribution network worst-case power noise and an efficient estimation method. In: Proc. 2014 IEEE 64th electronic components and technology conference (ECTC), vol 92617, Irvine, pp 2088–2093, DOI https://doi.org/10.1109/ECTC.2014.6897590

  17. Seo D, Lee H, Park M, Nah W (2018) Enhancement of differential signal integrity by employing a novel face via structure. IEEE Trans Electromagn Compat 60(1):26–33. https://doi.org/10.1109/TEMC.2017.2725943

    Article  Google Scholar 

  18. Shi H, Liu G, Liu A, Anil s P, Ng KS, Yew YH (2006) Simultaneous switching noise in FPGA and structure ASIC devices, methodologies for analysis, modeling, and validation. In: Proc. Electronic components and technology conference . https://doi.org/10.1109/ECTC.2006.1645652, pp 229–236

  19. Sjiariel R (2015) Power integrity simulation of power delivery network system. In: Proc. 2015 SBMO/IEEE MTT-S international microwave and optoelectronics conference (IMOC). https://doi.org/10.1109/IMOC.2015.7369185, pp 1–5

  20. Wang G (2018) A comprehensive study on LPDDR4X’s signal integrity and power integrity issues. PhD thesis, Xidian University, Xi’an

  21. Xu XM (2014) Inter-symbol interference and equivalent voltage noise of high-speed serial system. J Zhejiang Univ 48(1):118–123. https://doi.org/10.3785/j.issn.1008-973X.2014.01.018

    Article  Google Scholar 

  22. Yu P (2018) The analysis of PDN power supply noise in high speed circuits and the design of the decoupling networks. PhD thesis, Xidian University, Xi’an

  23. Zhang R, Gao N (2017) A design of 3D-SiP ceramic package based on signal/power integrity. Electron Packag 17:1–6. https://doi.org/10.16257/j.cnki.1681-1070.2017.0001

    Article  Google Scholar 

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Acknowledgements

This work was supported by the Tianjin Research Program of Application Foundation and Advanced Technology under Grant 17ZXRGGX00040.

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Correspondence to Han Wang.

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Responsible Editor: M. Abadir

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The authors are with Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, School of Microelectronics, Tianjin University, Tianjin, 300072, China.

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Yu, D., Wang, H. & Xu, J. Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation. J Electron Test 36, 365–374 (2020). https://doi.org/10.1007/s10836-020-05875-4

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