Abstract
Reversible Logic is one of the emerging technologies that has the capability of replacing traditional irreversible systems. The power consumption is low by the elimination of power dissipation caused by information loss in quantum computing. It is predicted that a high failure rate for future technologies increases demand for fault-tolerant in reversible logic. Safety and critical circuits employ redundancy in their designs to overcome any faults of the circuit during the normal operation. One of the most common forms to design fault-tolerant systems is to incorporate hardware redundancy to form N-Modular Redundancy (NMR), where N replicas of a module are connected to majority voters. In this paper, techniques for fault-masking have been proposed to prevent error propagation for reversible circuits by different implementations of the 3 and 5 input reversible majority voters. Both these voters are able to provide fault location information by using the techniques of insertion directly and independent and by taking advantage of available garbage outputs. The proposed reversible majority voters are efficient to deal with the single point of failure. Moreover, a novel design for 5-input reversible majority voter (MV5) is also presented. The structure of the proposed 5-input reversible majority voter is very simple and easy to implement in the reversible circuit. Evaluation results show that the proposed reversible MV5 can reduce the quantum cost up to 44% in the literature.
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References
Arabzadeh M, Zamani M, Sedighi M, Saeedi M (2011) Logical-depth-oriented reversible logic synthesis. In Proceedings of the International Workshop on Logic and Synthesis
Babu HMH, Chowdhury AR (2005) Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. In Proc. 18th international conference on VLSI design held jointly with 4th international conference on embedded systems (pp. 255-260). IEEE
Babu HMH, Islam MR, Chowdhury AR, Chowdhury SMA (2003) Reversible logic synthesis for minimization of full-adder circuit. In Proc. Euromicro symposium on digital system design (pp. 50-54). IEEE
Babu HMH, Mia MS, Biswas AK (2017) Efficient techniques for fault detection and correction of reversible circuits. J Electron Test 33(5):591–605
Bahar AN, Waheed S (2016) Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata. SpringerPlus 5(636):1–10
Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17(6):525–532
Boykin PO, Roychowdhury VP (2005) Reversible fault-tolerant logic. In Proc. international conference on dependable systems and networks (DSN'05) (pp. 444-453). IEEE
Choudhary J, Balasubramanian P, Varghese DM, Singh DP, Maskell D (2019) Generalized majority voter design method for N-modular redundant systems used in mission-and safety-critical applications. Computers 8(1):10
de Almeida AA, Dueck GW, da Silva ACR (2019) Efficient realization of Toffoli and NCV circuits for IBM QX architectures. In Proc. international conference on reversible computation (pp. 131-145). Springer
Donald J, Jha NK (2008) Reversible logic synthesis with Fredkin and Peres gates. ACM Journal on Emerging Technologies in Computing Systems (JETC) 4(1):1–19
Gaur HM, Singh AK, Ghanekar U (2015) A review on online testability for reversible logic. Procedia Computer Science 70:384–391
Gaur HM, Singh AK, Ghanekar U (2018) Offline testing of reversible logic circuits: an analysis. Integration 62:50–67
Haghparast M, Bolhassani A (2016) Optimization approaches for designing quantum reversible arithmetic logic unit. Int J Theor Phys 55(3):1423–1437
Handique M, Biswas S, Deka JK (2019) Test generation for bridging faults in reversible circuits using path-level expressions. J Electron Test 35(4):441–457
Jaiswal R, Sasamal TN (2017) Efficient design of exclusive-OR gate using 5-input majority gate in QCA. In IOP conference series: materials science and engineering (Vol. 225, no. 1, p. 012143). IOP publishing
Jayashree HV, Thapliyal H, Arabnia HR, Agrawal VK (2016) Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier. J Supercomput 72(4):1477–1493
Kalantari Z, Eshghi M, Mohammadi M, Jassbi S (2019) Low-cost and compact design method for reversible sequential circuits. J Supercomput 75(11):7497–7519
Khan MH, Rice JE (2018) First steps in creating online testable reversible sequential circuits. VLSI Design 2018:1–13
Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191
Mack C (2015) The multiple lives of Moore's law. IEEE Spectr 52(4):31–37
Miller DM, Wille R, Sasanian Z (2011) Elementary quantum gate realizations for multiple-control Toffoli gates. In Proc. 41st IEEE international symposium on multiple-valued logic (pp. 288-293)
Mohammadi M, Eshghi M (2009) On figures of merit in reversible and quantum logic designs. Quantum Inf Process 8(4):297–318
Mohammadi Z, Mohammadi M (2011) Fault tolerant reversible QCA design using TMR and fault detecting by a comparator circuit. Journal of Advances in Computer Research 2(4):71–80
Nashiry MA, Rice JE (2017) A reversible majority voter circuit and applications. In Proc. IEEE Pacific rim conference on communications, computers and signal processing (PACRIM) (pp. 1-6)
Nashiry MA, Rice JE (2019) Achieving fault tolerance in reversible computing. International Journal of Scientific & Engineering Research 10(5):52–56
Nashiry MA, Bhaskar GG, Rice JE (2015) Online testing for three fault models in reversible circuits. In Proc. IEEE international symposium on multiple-valued logic (pp. 8-13)
Nashiry MA, Khan MH, Rice JE (2017) Controlled and uncontrolled SWAP gates in reversible logic synthesis. In Proc. international conference on reversible computation (pp. 141-147). Springer
Nayeem NM, Rice JE (2013) Online testable approaches in reversible logic. J Electron Test 29(6):763–778
Pan WD, Nalasani M (2005) Reversible logic. IEEE Potentials 24(1):38–41
Saeedi M, Zamani MS, Sedighi M (2007) On the behavior of substitution-based reversible circuit synthesis algorithms: investigation and improvement. In Proc. computer society annual symposium on VLSI (ISVLSI'07) (pp. 428-436)
Thapliyal H, Ranganathan N (2010) Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM Journal on Emerging Technologies in Computing Systems (JETC) 6(4):1–31
Wille R, Große D, Teuber L, Dueck GW, Drechsler R (2008) RevLib: an online resource for reversible functions and reversible circuits. In Proc. 38th international symposium on multiple valued logic (pp. 220-225). IEEE
Zamani M, Farazmand N, Tahoori MB (2011) Fault masking and diagnosis in reversible circuits. In Proc. sixteenth IEEE European test symposium (pp. 69-74)
Zhong J, Muzio JC (2006) Analyzing fault models for reversible logic circuits. In Proc. IEEE international conference on evolutionary computation (pp. 2422-2427)
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Kheirandish, D., Haghparast, M., Reshadi, M. et al. Efficient Designs of Reversible Majority Voters. J Electron Test 36, 757–770 (2020). https://doi.org/10.1007/s10836-020-05912-2
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DOI: https://doi.org/10.1007/s10836-020-05912-2