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Fault-Aware Dependability Enhancement Techniques for Phase Change Memory

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Abstract

A variety of resistive memories have been proposed in recent years. Among these emerging technologies, phase change memory (PCM) has received the most research attentions since it has the advantages of high scalability, non-volatility, fast access, strong data retention, low cost, and low power consumption. It is also considered as the most promising alternative of DRAM. In order to conquer the inevitable endurance problem of PCM cells which causes serious reliability and yield threats, hard repair and ECC (Error correction code) techniques are widely adopted. However, since soft errors are not a main threat for PCM, incorporating ECC for each data word is not a cost-effective technique since a lot of memory space is required for storing the check bits. In this paper, the progressive ECC techniques including the local progressive ECC (LPE) technique and the global progressive ECC (GPE) technique are proposed to solve this dilemma. The key innovation is to equip ECC for a data word when its first faulty cell is detected. In other words, we only equip fault detection code for data words such that the original code rate can be increased significantly. An ECC DRAM and an ECC CAM are used for storing check bits and accessing purposes, respectively. Hardware architectures for implementing the proposed GPE and LPE techniques are also provided. A simulator is developed for evaluating repair rate, reliability, yield, and hardware overhead. According to experimental results, the degradation of repair rate and reliability are almost negligible. However, the hardware overhead is at least 80% lower than the original ECC technique while maintaining the original reliability and yield levels.

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Funding

This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Grant 108–2221-E-011–135.

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Authors and Affiliations

  1. National Taiwan University of Science and Technology, Taipei, Taiwan

    Shyue-Kung Lu & Hui-Ping Li

  2. Dept. Creative Informatics, Kyushu Institute of Technology, Fukuoka, Japan

    Kohei Miyase

  3. Industrial Technology Research Institute, Hsinchu, Taiwan

    Chun-Lung Hsu & Chi-Tien Sun

Authors
  1. Shyue-Kung Lu
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  2. Hui-Ping Li
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  3. Kohei Miyase
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  4. Chun-Lung Hsu
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  5. Chi-Tien Sun
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Correspondence to Shyue-Kung Lu.

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Responsible Editor: N. A. Touba

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Lu, SK., Li, HP., Miyase, K. et al. Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. J Electron Test 37, 503–513 (2021). https://doi.org/10.1007/s10836-021-05961-1

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  • DOI: https://doi.org/10.1007/s10836-021-05961-1

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