Abstract
As the scale of integrated circuits continues to increase and their test cost increases with test time, how to optimize the test parameters is an important topic. In analog integrated circuits, the implicit dependency among test parameters makes it possible to apply the XGBoost technique based on decision trees in machine learning to optimize the test parameters. In this paper, an optimization algorithm is proposed based on the XGBoost decision tree model. By modeling the representational relationships of each test parameter in the historical test data set, the list of those to be optimized is obtained according to the descending order of the escape rate in the prediction results. According to this list, the test parameters to be deleted are selected in turn, the prediction results of the remaining test parameters on those test parameters are obtained, and the escape rate after screening out the target parameters is evaluated, and the test parameters are optimized based on this list to reduce the test time and test cost.
Similar content being viewed by others
Data Availability
The data that support the findings of this study are available from [Xi’an Microelectronic Technology Institute] but restrictions apply to the availability of these data, which were used under license for the current study, and so are not publicly available. Data are however available from the authors upon reasonable request and with permission of [Xi’an Microelectronic Technology Institute].
References
Amati L, Bolchini C, Salice F (2011) Optimal test set selection for fault diagnosis improvement. In: Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp 93–99
Benner S, Boroffice O (2001) Optimal production test times through adaptive test programming. In: Proceedings International Test Conference 2001 (Cat. No. 01CH37260), IEEE, pp 908–915
Bergstra J, Bardenet R, Bengio Y, Kégl B (2011) Algorithms for hyper-parameter optimization. Adv Neural Inf Process Syst 24
Bergstra J, Yamins D, Cox D (2013) Making a science of model search: Hyperparameter optimization in hundreds of dimensions for vision architectures. In: Proc. International Conference on Machine Learning, PMLR, pp 115–123
Biswas S, Blanton RD (2006) Statistical test compaction using binary decision trees. IEEE Des Test Comput 23(6):452–462
Breiman L (2001) Random forests. Mach Learn 45(1):5–32
Brockman JB, Director SW (1989) Predictive subset testing: Optimizing IC parametric performance testing for quality, cost, and yield. IEEE Trans Semicond Manuf 2(3):104–113
Chen M, Orailoglu A (2008) Test cost minimization through adaptive test development. In: Proc. IEEE International Conference on Computer Design, pp 234–239
Chen T, Guestrin C (2016) Xgboost: A scalable tree boosting system. In: Proceedings of the 22nd acm sigkdd international conference on knowledge discovery and data mining, pp 785–794
Chen W (2014) The optimization study about improving the IC testing yield and reduce the testing time. Master’s thesis, University of Electronic Science and Technology of China
Hastie T, Tibshirani R, Friedman J, Franklin J (2005) Reviews-the elements of statistical learning: data mining, inference and prediction. Math Intell 27(2):83–84
Higami Y, Saluja KK, Takahashi H, Kobayashi Sy, Takamatsu Y (2006) Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. In: Proc. Asia and South Pacific Conference on Design Automation, 2006., IEEE, pp 6–pp
Hou W, Liang H, Song T et al (2021) Integrated circuit test method based MRMR algorithm and BP neural network. Microelectronics 51(5):766
Jiang W, Vinnakota B (2001) Defect-oriented test scheduling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(3):427–438
Li Y, Yilmaz E, Sarson P, Ozev S (2018) Online information utility assessment for per-device adaptive test flow. In: Proc. IEEE 36th VLSI Test Symposium (VTS), pp 1–6
Li Y, Yilmaz E, Sarson P, Ozev S (2019) Adaptive test for RF/analog circuit using higher order correlations among measurements. ACM Transactions on Design Automation of Electronic Systems (TODAES) 24(4):1–16
Liaw R, Liang E, Nishihara R, Moritz P, Gonzalez JE, Stoica I (2018) Tune: A research platform for distributed model selection and training. arXiv preprint arXiv:180705118
Milor L, Sangiovanni-Vincentelli A (1994) Minimizing production test time to detect faults in analog circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 13(6):796–813. https://doi.org/10.1109/43.285252
Shukoor MA, Agrawal VD (2009) A two phase approach for minimal diagnostic test set generation. In: Proc. 14th IEEE European Test Symposium, pp 115–120
Stratigopoulos HG (2018) Machine learning applications in IC testing. In: Proc. IEEE 23rd European Test Symposium (ETS), pp 1–10
Stratigopoulos HG, Drineas P, Slamani M, Makris Y (2007) Non-RF to RF test correlation using learning machines: A case study. In: Proc. 25th IEEE VLSI Test Symposium (VTS’07), pp 9–14
Stratigopoulos HG, Drineas P, Slamani M, Makris Y (2009) Rf specification test compaction using learning machines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(6):998–1002
Vinayak RK, Gilad-Bachrach R (2015) Dart: Dropouts meet multiple additive regression trees. In: Artificial Intelligence and Statistics, PMLR, pp 489–497
Wang L, Luo M (2019) Machine learning applications and opportunities in IC design flow. In: Proc. International Symposium on VLSI Design. Automation and Test (VLSI-DAT), IEEE, pp 1–3
Yi M, Song C, Yu J, et al. (2021) An adaptive test method of IC based on random forest. Journal of Zhengzhou University (Engineering Science) 42(4):6
Yilmaz E, Ozev S (2008) Dynamic test scheduling for analog circuits for improved test quality. In: Proc. IEEE International Conference on Computer Design, pp 227–233
Yilmaz E, Ozev S (2009) Adaptive test elimination for analog/RF circuits. In: Proc. 46th ACM/IEEE Design Automation Conference, pp 720–725
Zhang SH (2011) The application of ping-pong mode in IC production test. China Integrated Circuit 20(12):5
Acknowledgments
This work was supported by the National Natural Science Foundation of China under Grant 61871089 and Key Laboratory of Automatic Testing Technology and Instruments under Grant YQ201202.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflicts of Interests
The authors declare there is no conflicts of interest regarding the publication of this paper.
Additional information
Responsible Editor: M. Sachdev
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Xiao, Y., Zeng, Y., Wu, Q. et al. Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost. J Electron Test 38, 279–288 (2022). https://doi.org/10.1007/s10836-022-06009-8
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-022-06009-8