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Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications

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Abstract

Hardware security has become most prevalent challenging concept of improving the Internet of Things (IoT) in human routine as well as in future engineering processes. IoT systems face a wide range of problems, including a dearth of resources, a requirement for equipment protection from cyber-attacks, and lower power consumption. Especially, the methods are constrained by power consumption and an insufficient of computing capacity. Moreover, the customary method of keeping secret keys in non-volatile memory is susceptible to assaults like side-channelling and reverse engineering. Physical Unclonable Functions (PUFs) are a technique for improving security of physical device and resolving difficulties with current cryptographic algorithms. PUFs are simple operations that force each terminal to have a unique personality based on physical characteristics imposed during production that are unpredictable and impossible to replicate. The focus of this work is on XOR arbiter PUF (XORAPUF) architecture with the three factors: reliability, uniqueness, and uniformity. Experiments show that the proposed XORAPUF implemented on field programmable gate array (FPGA) achieves inter-chip hamming distance (HD) closer to 50% with excellent uniqueness and uniformity of 49.88% and 48.74%, respectively. The reliability of the designed PUF is also optimized to 99.20%. On comparing the designed PUF metrics results with conventional PUF, the XORAPUF circuit generated better results.

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Authors and Affiliations

  1. Research Scholar, Dept. of ECE, Karunya Institute of Technology and Sciences, Tamilnadu, Coimbatore, 641114, India

    R. Naveenkumar & A. Napolean

  2. Dept. of ECE, Karunya Institute of Technology and Sciences, Tamilnadu, Coimbatore, 641114, India

    N. M. Sivamangai & S. Sridevi Sathya Priya

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  1. R. Naveenkumar
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  2. N. M. Sivamangai
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  3. A. Napolean
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  4. S. Sridevi Sathya Priya
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The first author wrote the manuscript, and the second author supervised, third and fourth author- done the proof reading.

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Correspondence to R. Naveenkumar.

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Naveenkumar, R., Sivamangai, N.M., Napolean, A. et al. Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications. J Electron Test 38, 653–666 (2022). https://doi.org/10.1007/s10836-022-06034-7

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