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Optimal wafer cutting in shuttle layout problems

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Abstract

A major cost in semiconductor manufacturing is the generation of photo masks which are used to produce the dies. When producing smaller series of chips it can be advantageous to build a shuttle mask (or multi-project wafer) to share the startup costs by placing different dies on the same mask. The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible dies can be cut from a given wafer, and each cutting plan must respect various constraints on where the cuts may be placed. We present an exact algorithm for solving the minimum cutting plan problem, given a floorplan of the dies. The algorithm is based on delayed column generation, where the pricing problem becomes a maximum vertex-weighted clique problem in which each clique consists of cutting compatible dies. The resulting branch-and-price algorithm is able to solve realistic cutting problems to optimality in a couple of seconds.

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References

  • Andersson M, Levcopoulos C, Gudmundsson J (2005) Chips on wafers. Comput Geom Theory Appl 30:95–111

    Article  MathSciNet  MATH  Google Scholar 

  • Balas E, Chvatal V, Nesetril J (1987) On the maximum weight clique problem. Math Oper Res 12(3):522–535

    Article  MathSciNet  MATH  Google Scholar 

  • Carraghan R, Pardalos P (1990) An exact algorithm for the maximum clique problem. Oper Res Lett 9:375–382

    Article  MATH  Google Scholar 

  • Chen S, Lynn EC (2003) Effective placement of chips on a shuttle mask. In: Proc of SPIE, vol 5130, pp 681–688

  • Chen C-C, Mak W-K (2006) A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. In: Asian and South Pacific design automation conference

  • Gilmore PC, Gomory RE (1961) A linear programming approach to the cutting-stock problem. Oper Res 9(6):849–859

    Article  MathSciNet  MATH  Google Scholar 

  • Kahng AB, Mandoiu I, Wang Q, Xu X, Zelikovsky AZ (2004) Multi-project reticle floorplanning and wafer dicing. In: Proc of ISPD, pp 70–77

  • Lougee-Heimer R (2003) The Common Optimization INterface for Operations Research: promoting open-source software in the operations research community. IBM J Res Dev 47(1):57–66

    Article  Google Scholar 

  • Nisted L (2006) Solving the shuttle layout problem using decomposition. Technical Report 06-02-6 (D Pisinger, supervisor), DIKU, University of Copenhagen, Denmark

  • Östergård PRJ (2001) A new algorithm for the maximum-weight clique problem. Nord J Comput 8(4):424–436

    MATH  Google Scholar 

  • Östergård PRJ (2002) A fast algorithm for the maximum clique problem. Discrete Appl Math 120(1–3):197–207

    Article  MathSciNet  MATH  Google Scholar 

  • Vazirani VV (2003) Approximation algorithms. Springer, Berlin

    Google Scholar 

  • Wolsey LA (1998) Integer programming. Wiley-Interscience, New York

    MATH  Google Scholar 

  • Wu M-C, Lin R-B (2005) Reticle floorplanning and wafer dicing for multiple project wafers. In: ISQED 2005, pp 610–615

  • Xu G, Tian R, Wong DF, Reich A (2003) Shuttle mask floorplanning. In: Proc of SPIE, vol 5256, pp 185–194

  • Xu G, Tian R, Pan DZ, Wong MDF (2004) A multi-objective floorplanner for shuttle mask optimization. In: Proc SPIE, vol 5567, pp 340–350

  • Xu G, Tian R, Pan DZ, Wong MDF (2005) CMP aware shuttle mask floorplanning. In: Asian and South Pacific design automation conference

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Correspondence to David Pisinger.

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Nisted, L., Pisinger, D. & Altman, A. Optimal wafer cutting in shuttle layout problems. J Comb Optim 22, 202–216 (2011). https://doi.org/10.1007/s10878-009-9284-z

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  • DOI: https://doi.org/10.1007/s10878-009-9284-z

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