Abstract
Interconnect shielding is used in VLSI designs to avoid noise interference from the cross-coupling capacitance between adjacent signals. This paper takes advantage of the shields already present in the design and uses them to tune the propagation delay of the clock signals, thus eliminating expensive dedicated delay buffers. The problem of obtaining the desired delay at a minimum shielding cost (silicon area) is formulated as a calculus of variations problem. An analytical solution shows that a square root shield profile is optimal.
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Acknowledgments
The authors are thankful for the useful comments and corrections made by the editor Prof. D. Hull. This research was supported by the Office of the Israeli Chief Scientist under the HiPer consortium of the MAGNET program.
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Communicated by David G. Hull.
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Frankel, B., Wimer, S. Optimal VLSI Delay Tuning by Wire Shielding. J Optim Theory Appl 170, 1060–1067 (2016). https://doi.org/10.1007/s10957-016-0960-8
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DOI: https://doi.org/10.1007/s10957-016-0960-8