Skip to main content
Log in

Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application

  • Published:
Mobile Networks and Applications Aims and scope Submit manuscript

Abstract

The wireless network (WN) has become an integral part of the living habits of human beings. Most of the crypto chips are broadly utilized in WN application to assure the security of information. The functional correctness of cryptographic devices should be verified to authenticate the precision of the secrecy of the information. In the IC industry correctness of the wireless sensing device can be verified by scan design-based testing. The scan chain-based testing is the most popularly used testing technique due to its increased fault coverage and improved test quality. It also acts as a hacking tool and recovers sensitive data through side-channel attacks like power, time, or hamming distance. This paper presents the state-of-art-of secure mechanism to protect the scan chain from the side-channel attack using the obfuscation technique and logic locking Scheme. The proposed methodology provides direct access to internal data to the authorized test engineer. Although, the security synthesis creates a controllable confusion between the reverse-engineered netlist and the original design. The proposed secure design protects the design from a hamming distance-based attack, brute force attack, and hill-climbing attack. Then evaluate the security and overhead of the suggested approach using ISCAS’89 and ITC’99 test circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Xie H, Yan Z, Yao Z, Atiquzzaman M (2019) Data collection for security measurement in wireless SensorNetworks: a survey. IEEE Internet Things J 6:2205–2224

    Article  Google Scholar 

  2. Wang J, Gao Y, Liu W, Wu W, Lim SJ (2019) An asynchronous clustering and mobile data gathering Schema based on timer mechanism in wireless sensor networks. CMC Comput Mater Contin 58:711–725

    Google Scholar 

  3. Hely D, Flottes M-L, Bacel F, Rouzeyre B, Berard N, Renovell M (2004) Scan design and secure chip [secure IC testing]. 10th IEEE On-Line Testing and Robust SystemDesign (IOLTS ) Proceeding 21:9–224

    Google Scholar 

  4. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, Norwell

    Google Scholar 

  5. Ali SS, OzgurSinanoglu SM, Saeed RK (2013) New scan-based attack using only the test mode. In: 21st IFIP/IEEE International Conference on Very Large Scale Integration, pp 234–239

    Google Scholar 

  6. Lee J, Tehranipoor M, Patel C, Plusquellic J (2005) Securing scan design using Lock & key Technique. In: International Symposium on Defect and Fault Tolerance in VLSI System, pp 51–62

    Google Scholar 

  7. Paul S, Chakraborty R, Bhunia S (2004) VIm-scan, a low overhead scan design approach for the protection of secret key in scan-based secure chips. In: Proceedings of 25th IEEE VLSI Test Symposium, pp 455–460

    Google Scholar 

  8. Fujiwara K, Fujiwara H, Tamamoto H (2010) SREEP-2: SR- equivalent generator for secure and testable scan design. In: 11th IEEE Workshop on RTL and High-Level Testing, pp 7–12

    Google Scholar 

  9. Das A, Karaklajic D, Verbauwhede I (2014) Secure mutual testing strategy for cryptographic SoCs. IACR Cryptol. ePrint Arch., 2014, 544

  10. Ali SS, Saeed SM, Sinanoglu O, Karri R (2015) Novel test-mode- only scan attack and countermeasure for compression-based scan architectures. IEEE Trans Comput-Aided Design Integr Circuits Syst 34(5):808_821

    Article  Google Scholar 

  11. Senegar G, Mukhopadhyay D, Chowdhruy DR (2007) Secureflipped scan-chain model for crypto- architecture. IEEE transactions on Computer-Aided Design of Integrated Circuits andSystems 2(11):2080–2084

    Article  Google Scholar 

  12. Da Rolt J, Di Natale G, Flottes M, Rouzeyre B (2011) Scan attack and countermeasures in the presence of scan response compactors. In: Proceedings of 16thIEEE European Test Symposium (ETS), pp 19–24

    Google Scholar 

  13. Shafik RA, Mathew J, Pradhan DK (2015) A low-cost unified design methodology for secure test and intellectual property Core protection. IEEE Transaction on Reliability 64:1243–1125

    Article  Google Scholar 

  14. Silva MD, Flottes M-L, Natale GD, Rouzeyre B, Prinetto P, Restifo M (2017) Scan chain encryption for the test, diagnosis and debug of secure circuits. In: in Proc. 22nd IEEE Eur. Test Symp. (ETS), pp 1–6

    Google Scholar 

  15. Zhang J (2016) A practical logic obfuscation technique for hardware security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24(3):1193–1197

    Article  Google Scholar 

  16. Rahman MT, Rahman MS, Wang H, Tajik S, Khalil W, Farahmandi F, Tehranipoor M (2020) Defense-in-depth: a recipe for logic locking to prevail. Integration 72:39–57

  17. Bhakthavatchalu R, Kannan SK, Nirmala Devi M (2015) Verilog design of programmable JTAG controller for digital VLSI ICs. Indian J Sci Technol 8:17

    Article  Google Scholar 

  18. Sankaralingam R, Oruganti RR, Touba NA (2000) Static compaction techniques to control scan vector power dissipation. In: Proc. of VLSI Test Symposium, Montreal, pp 35–34

    Chapter  Google Scholar 

  19. Shi Y, NozomuTogawa MY, Ohtsuki T (2012) Robust secure scan design against scan-based differential cryptanalysis. IEEE Transactions on Very LargeScale Integration (VLSI) systems 20:176–181

    Article  Google Scholar 

  20. Inoue M, Yoneda T, Hasegawa M, Fujiwara H (2011) Balanced secure scan: partial ScanApproach for secret information protection. Journal of Electronic Testing: Theory and Applications (JETTA) 27(2):99–108

    Article  Google Scholar 

  21. Chandran U, Zhao D (2009) SS-KTC: a high-testability low-overhead scan architecture with multi-level security integration. In: Proceedings of VLSI test symposium, pp 321–326

    Google Scholar 

  22. Razzaq M, Singh V, Singh A (2011) SSKTR: secure and testable scan design through test key randomization. Proc Asian Test Symp 33:60–65

    Google Scholar 

  23. Mukhopadhyay D, Banerjee S, RoyChowdhury D, Bhattacharya BB (2005) CryptoScan ASecured scan chain architecture. In: Proceedings of the 14th Asian Test Symposium, pp 348–353

    Google Scholar 

  24. Novak F, Biasizzo A (2006) Security extension for IEEE std 1149.1. J Electron Test 22:301–303

    Article  Google Scholar 

  25. Shiny MI, Nirmala DM (2017) LFSR based secured scan design testability techniques. Proc Comput Sci 115:174–181

    Article  Google Scholar 

  26. Kumar KV, Jayasankar T, Eswaramoorthy V, Nivedhitha V (2020) SDARP: security based data aware routing protocol for ad hoc sensor networks. Int J Intel Netw 1:36–42

    Google Scholar 

  27. Wang X, Zhang D, He M, Su D, Tehranipoor M (2018) Secure scan and test using obfuscation throughout supply chain. IEEE Trans Comput- Aided Design Integr Circuits Syst 37(9):1867–1880

    Article  Google Scholar 

  28. Wang W, Deng Z, Wang J (2019) Enhancing sensor network security with improved internal hardware design. J Sensors Vol:1752

    Article  Google Scholar 

  29. Vaghani D, Ahlawat S, Tudu J, Fujita M, Singh V (2018) On securing scan design through test vector encryption. In: Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp 1–5

    Google Scholar 

  30. Saleem MA, Bhardwaj R, Datta D (2020) Application of intelligent computing to develop performance index algorithm as a multicriteria decision making tool. Int J Intel Netw 1:85–91

    Google Scholar 

  31. Hely D, Rosenfeld K, Karri R (2011) Security challenges during VLSI test. In: Proceedings of IEEE New Circuits and Systems Conference (NEWCAS), pp 486–489

    Google Scholar 

  32. Daniel G, Costa SF, Oliveira G (2017) cryptography in wireless multimedia sensor networks: a survey and research directions. J Crypto 1(4):1–18

    Google Scholar 

  33. Remy M, Prabhu E, Mangalam H (2014) A versatile low power Design of bit-Serial Multiplier in finite fields GF (2m). In: Proceedings of the IEEE International Conference on Communication and Signal Processing (ICCSP), April, pp 474–478

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to M. I. Shiny.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Shiny, M.I., Nirmala Devi, M. Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application. Mobile Netw Appl 27, 1000–1018 (2022). https://doi.org/10.1007/s11036-021-01857-8

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11036-021-01857-8

Keywords

Navigation