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A hierarchical multiplier-free architecture for HEVC transform

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Abstract

In spite of high decorrelation performance, the large block size of transform coding in High Efficiency Video Coding (HEVC) brings about undesirable complexity in hardware design. The heaviest burden in HEVC transform implementation is the large quantity of multiplications. In this paper, we propose a novel hierarchical multiplier-free architecture for HEVC transform, which can achieve a multiplier-free partial butterfly combined with matrix multiplications (PBMM) architecture based on vector decomposition (VD-PBMM). In the proposed architecture, the complicate matrix multiplication in PBMM is achieved by several simple stages to simplify its VLSI realization. Each stage only involves additions and multiplications with power of two which can be achieved by shifters and adders. In addition, the new architecture can balance the distribution of adders to improve the system frequency. The proposed architecture has been evaluated with TSMC 0.13um CMOS technology. The relative system can run at 400 MHz with 92 K logic gates, which is about half of the PBMM method when the latency is 8. The proposed architecture can achieve the transform without any performance loss compared with the standard, and it is suitable for the hardware implementation in VLSI design.

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Acknowledgments

This work was supported in part by the NSFC (No. 61227004,61100155,61401333 and 61301288), the Fundamental Research Funds of the Central Universities of China (No. K5051302096, K5051399020, K5051202050, and JB140207), and the Research Fund for the Doctoral Program of Higher Education (No. 20130203130001).

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Authors and Affiliations

  1. Key Laboratory of Intelligent Perception and Image Understanding (Chinese Ministry of Education), School of Electronic Engineering, Xidian University, Xi’an, China

    Chunxiao Fan, Fu Li, Guangming Shi, Yi Niu, Fei Qi, Xuemei Xie & Dandan Jiao

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  1. Chunxiao Fan
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  2. Fu Li
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  3. Guangming Shi
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  7. Dandan Jiao
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Correspondence to Fu Li.

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Fan, C., Li, F., Shi, G. et al. A hierarchical multiplier-free architecture for HEVC transform. Multimed Tools Appl 76, 997–1015 (2017). https://doi.org/10.1007/s11042-015-3114-3

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  • DOI: https://doi.org/10.1007/s11042-015-3114-3

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