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An embedded multimedia communication terminal based on DSP+FPGA

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Abstract

The main content of this paper is the embedded multimedia terminal circuit design and the research and implementation of video image correlation algorithm based on Embedded Multimedia processor. The specific research contents include the design of embedded multimedia design, driving circuit of embedded multimedia DSP and the real-time performance of the algorithm based on the DSP program design. In this paper, the design of multimedia terminal circuit embedded multimedia DSP based on FPGA structure, including the design, multimedia DSP driver design and implementation of video algorithm. The embedded multimedia terminal with embedded multimedia DSP and FPGA structure, multimedia DSP as the main control CPU, responsible for functions such as audio and video collection, video display, signal processing and network communication; FPGA is used to realize the control logic and VGA and composite video switching circuit and video format conversion function. The embedded multimedia terminal has two video input; a video VGA and composite video optional output; stereo audio input and output; Ethernet communication function.

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References

  1. (2009) Samsung.TMS320C6713 DSP technology principle and application. Beijing: Electronic Industry Press

  2. Csaba B (2008) Bayesian foreground and shadow detection in uncertain frame rate surveillance videos [J]. IEEE Trans Image Process 17(4):608–621

    Article  MathSciNet  Google Scholar 

  3. Dong X et al (2005) Insignificant shadow detection for video segmentation [J]. IEEE Trans Circuits Syst Video Technol 15(8):1058–1064

    Article  Google Scholar 

  4. Girardi A (2008) A modified IBIS model aimed at signal integrity analysis of systems in package [J]. IEEE Trans Circuits Syst 55(7):1921–1928

    Article  MathSciNet  Google Scholar 

  5. Haoyu (2012) A High-quality and high-speed system of bayer image restoration controlled by DM642 and FPGA[C]. Int Conf Measure Inf Control 2012:935–938

    Google Scholar 

  6. IS42S16400B 1MegBits × 16Bits × 4Banks (64-MBIT) Synchronous dynamic ram datasheet [EB/OL]. Feb. 2005(Rev. D). http://www.issi.com.

  7. Kaihua X (2009) Signal integrity research of high speed circuit of embedded system[C]. Front Comput Sci Technol, 2009. FCST '09. 473–477

  8. Kunhe L et al (2010) Implementation and optimization of a weed identification algorithm on the DSP with C64+ core[C]. Intell Signal Process Commun Syst 825–828

  9. Liu X (2007) DSP and FPGA-based video processing system design and its implementation [J]. Laser Infrared 37(12):1328–1330

    Google Scholar 

  10. Liu Y-b (2011) The design of IP videophone based on TMS320DM642[C]. 2011 Fourth international conference on intelligent computation technology and automation. 757–760

  11. Ma H (2006) Embedded system design guide [M]. Electronic Industry Press

  12. Masada E, Yoshinaga J (2001) Communication technology. Science Press, Beijing

    Google Scholar 

  13. Ti, Inc.TMS320DM642 video/imaging fixed-point digital signal processor [EB/OL]. 2010 (Rev.D).http://www.ti.com/product/sm320dm642-ep

  14. Ti, TMS320C64x image/video processing library programmer’s reference [EB/OL]. Literature Number: SPRU023B: 2003. http://www.ti.com

  15. Wang Y, Liu J (2009) The design and development of.TMS320DM643DSP application system. People’s Posts and Telecommunications Publishing House. Agency, Beijing

    Google Scholar 

  16. Xu Z (2009) Design of DM642 video decoding device driver based on TVP5150[J]. Electron Device 29(3):945–950

    Google Scholar 

  17. Yang Y (2007) A fast algorithm for YCbCr to RGB conversion[C]. IEEE Trans Consum Electron 53(4):1490–1493

    Article  Google Scholar 

  18. Yu FQ (2008) Principle and structure design (Chinese Edition). TMS320 C6000 DSP. Beihang University press, Beijing

  19. Zhou Q (2007) Quick look-up table to optimize video decoding YCbCr to RGB conversion [J]. Modern Electron Technol 15:167–169

    Google Scholar 

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Correspondence to Li Guo.

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Guo, L. An embedded multimedia communication terminal based on DSP+FPGA. Multimed Tools Appl 76, 16949–16961 (2017). https://doi.org/10.1007/s11042-016-3597-6

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  • DOI: https://doi.org/10.1007/s11042-016-3597-6

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