Abstract
Integral histogram provides efficient histogram computation for all possible target regions, and is widely applied in many computer vision tasks. In this paper, to address the intensive computation and frequent memory accessing bottleneck in real-time applications, a sliced integral histogram algorithm is proposed for efficient integral histogram computation. We explore how maximum parallel computation and storage reduction are simultaneously achieved. Hardware implementation architecture on Field-programmable gate array (FPGA) platform is presented. We also suggest criterion for the optimal number of slices, which allows the most appropriate architecture to be selected. Comparing with the state-of-the-art methods, experimental results on Cyclone platform demonstrate the validity of the proposed algorithm in terms of computation speed, storage capacity and power consumption. Meanwhile, the proposed algorithm can be extended to other histogram based feature descriptors and implemented on any parallel processing platforms.
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Acknowledgments
This work is supported by the National Natural Science Foundation of China (No. 61203239, 61305015), and Postdoctoral Science Foundation of China (No. 2015M580591). The authors would like to thank the associate editor and the reviewers for helpful comments that greatly improved this paper.
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Yang, Y., Liu, YX. & Dong, QF. Sliced integral histogram: an efficient histogram computing algorithm and its FPGA implementation. Multimed Tools Appl 76, 14327–14344 (2017). https://doi.org/10.1007/s11042-016-3816-1
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DOI: https://doi.org/10.1007/s11042-016-3816-1