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Efficient half-precision floating point multiplier targeting color space conversion

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Abstract

Color Space Conversion (CSC) in image processing applications, demands computationally simple floating point multipliers consuming less area and power. This necessitates the design and realization of the same meeting the aforesaid concerns. This paper makes one such contribution in the form of a New Bit Pair Recoding (NBPR) algorithm for realizing a Data Length Reduction (DLR)-based 16-bit Half-Precision Floating Point Multiplier (HPFPM). This algorithm with merged partial product addition achieves partial product height reduction from n to \(\frac {n}{4}\) for an n × n multiplier by evading 2’s complement, negative encoding and sign extension. HPFPM is implemented on both Application Specific Integration Circuit (ASIC) with TSMC 180, 130 and 65 nm technologies and Xilinx-Virtex-5 and Virtex-7 Field Programmable Gate Array (FPGA) families. HPFPM synthesized on TSMC 65nm consumes 51% and 55.8% of area and power respectively, with 0.6835% error when compared with full width half-precision multiplier. Also, HPFPM for RGB-YUV-RGB and RGB-YCbCr-RGB conversion reduces the area, power consumption by 11%, 12% respectively, with 93.2% improved accuracy, when compared with truncated 32-bit single-precision floating point multipliers (SPFPMs). The converted image is evaluated using Peak-Signal-to-Noise-Ratio (PSNR) and Mean Square Error (MSE) in Matlab for quantifying HPFPM suitability for CSC in imaging.

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  1. School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, Tamil Nadu, India

    J. Jean Jenifer Nesam & S. Sivanantham

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  1. J. Jean Jenifer Nesam
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  2. S. Sivanantham
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Correspondence to S. Sivanantham.

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Nesam, J.J.J., Sivanantham, S. Efficient half-precision floating point multiplier targeting color space conversion. Multimed Tools Appl 79, 89–117 (2020). https://doi.org/10.1007/s11042-019-08040-y

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  • DOI: https://doi.org/10.1007/s11042-019-08040-y

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