Abstract
This paper proposes hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. In this paper two types of dynamic reconfiguration for evolutionary algorithm are introduced. The processor was designed by using VHDL and the circuit was simulated. The effectiveness of the proposal processor was confirmed.
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This work was supported by Tokyo Denki University Science Promotion Fund (Q09-01).
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Kanasugi, A., Tsukahara, A. & Ando, K. Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. Nat Comput 14, 593–601 (2015). https://doi.org/10.1007/s11047-014-9476-z
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DOI: https://doi.org/10.1007/s11047-014-9476-z