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Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata

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Abstract

Complementary metal-oxide semiconductor (CMOS) technology may face so much problems in future due to the smaller size of transistors and increase in circuits’ volume and chips temperature. A new technology that can be a good alternative to CMOS circuits is quantum-dot cellular automata (QCA). These technologies have features such as a very low power consumption, high speed and small dimensions. In nano-communication system, error detection and correction in a receiver message are major factors. In addition, circuit reversibility in QCA helps designs a lot. In this research, generator and checker circuit of the reversible parity and eventually their nano-communication system are designed reversible using odd parity bit. The proposed circuits and the theoretical values are tested by QCADesigner 2.0.3 simulator to show the correct operation of the circuits. According to the simulation results, the proposed circuits compared with the previous structure improve delay by 90–75–35% in generator and checker structures of parity and their reversibility of nano-communication system, respectively. The proposed circuits are used in nano-transmitters and nano-receivers.

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References

  1. Asfestani, M.N., Heikalabad, S.R.: A novel multiplexer-based structure for random access memory cell in quantum-dot cellular automata. Phys. B Condens. Matter 521, 162–167 (2017)

    Article  Google Scholar 

  2. Das, J.C., De, D.: Circuit switching with quantum-dot cellular automata. Nano Commun. Netw. (2017). https://doi.org/10.1016/j.nancom.2017.09.002

    Google Scholar 

  3. Sen, B., Sahu, Y., Mukherjee, R., Nath, R.K., Sikdar, B.K.: On the reliability of majority logic structure in quantum-dot cellular automata. Microelectron. J. 47, 7–18 (2016)

    Article  Google Scholar 

  4. Hosseinzadeh, H., Heikalabad, S.R.: A novel fault tolerant majority gate in quantum-dot cellular automata to create a revolution in design of fault tolerant nanostructures, with physical verification. Microelectron. Eng. 192, 52–60 (2018). https://doi.org/10.1016/j.mee.2018.01.019

    Article  Google Scholar 

  5. Heikalabad, S.R., Navin, A.H., Hosseinzadeh, M.: Midpoint memory: a special memory structure for data-oriented models implementation. J. Circuits Syst. Comput. 24(5), 1550063 (2015)

    Article  Google Scholar 

  6. Heikalabad, S.R., Navin, A.H., Hosseinzadeh, M.: Content addressable memory cell in quantum-dot cellular automata. Microelectron. Eng. 163, 140–150 (2016)

    Article  Google Scholar 

  7. Tougaw, P.D., Lent, C.S.: Logical devices implemented using quantum cellular automata. J. Appl. Phys. 75(3), 1818–1825 (1994)

    Article  Google Scholar 

  8. Tougaw, P.D.: A device architecture for computing with quantum dots. Proc. IEEE 85(4), 541–557 (1997)

    Article  Google Scholar 

  9. Karkaj, E.T., Heikalabad, S.R.: Binary to gray and gray to binary converter in quantum-dot cellular automata. Opt. Int. J. Light Electron Opt. 130, 981–989 (2017). https://doi.org/10.1016/j.ijleo.2016.11.087

    Article  Google Scholar 

  10. Karkaj, E.T., Heikalabad, S.R.: A testable parity conservative gate in quantum-dot cellular automata. Superlattices Microstruct. (2016). https://doi.org/10.1016/j.spmi.2016.08.054

    Google Scholar 

  11. Gadim, M.R., Navimipour, N.J.: A new three-level fault tolerance arithmetic and logic unit based on quantum dot cellular automata. Microsyst. Technol. (2017). https://doi.org/10.1007/s00542-017-3502-x

    Google Scholar 

  12. Heikalabad, S.R., Asfestani, M.N., Hosseinzadeh, M.: A full adder structure without crosswiring in quantum-dot cellular automata with energy dissipation analysis. J. Supercomput. (2017). https://doi.org/10.1007/s11227-017-2206-4

    Google Scholar 

  13. Barughi, Y.Z., Heikalabad, S.R.: A three-layer full adder/subtractor structure in quantum-dot cellular automata. Int. J. Theor. Phys. 56, 2848 (2017). https://doi.org/10.1007/s10773-017-3453-0

    Article  MATH  Google Scholar 

  14. Rad, S.K., Heikalabad, S.R.: Reversible flip-flops in quantum-dot cellular automata. Int. J. Theor. Phys. 56, 2990 (2017). https://doi.org/10.1007/s10773-017-3466-8

    Article  MATH  Google Scholar 

  15. Sadoghifar, A., Heikalabad, S.R.: A content-addressable memory structure using quantum cells in nanotechnology with energy dissipation analysis. Phys. B Condens. Matter 537, 202–206 (2018). https://doi.org/10.1016/j.physb.2018.02.024

    Article  Google Scholar 

  16. Asfestani, M.N., Heikalabad, S.R.: A unique structure for the multiplexer in quantum dot cellular automata to create a revolution. Physica B Condens. Matter 512, 91–99 (2017). https://doi.org/10.1016/j.physb.2017.02.028

    Article  Google Scholar 

  17. Babaie, S., Sadoghifar, A., Bahar, A.N.: Design of an efficient multilayer arithmetic logic unit in quantum-dot cellular automata (QCA). IEEE Trans. Circuits Syst. II Express Briefs (2018)

  18. Salimzadeh, F., Heikalabad, S.R.: Design of a novel reversible structure for full adder/subtractor in quantum-dot cellular automata. Physica B Phys. Condens. Matter (2018). https://doi.org/10.1016/j.physb.2018.12.028

    Google Scholar 

  19. Heikalabad, S.R., Gadim, M.R.: Design of improved arithmetic logic unit in quantum-dot cellular automata. Int. J. Theor. Phys. 57(6), 1733–1747 (2018). https://doi.org/10.1007/s10773-018-3699-1

    Article  MathSciNet  MATH  Google Scholar 

  20. Kamrani, S., Heikalabad, S.R.: A unique reversible gate in quantum-dot cellular automata for implementation of four flip-flops without garbage outputs. Int. J. Theor. Phys. 57(11), 3340–3358 (2018). https://doi.org/10.1007/s10773-018-3847-7

    Article  MathSciNet  MATH  Google Scholar 

  21. Ahmadpour, S.S., Mosleh, M., Heikalabad, S.R.: A revolution in nanostructure designs by proposing a novel QCA full-adder based on optimized 3-input XOR. Physica B 550, 383–392 (2018). https://doi.org/10.1016/j.physb.2018.09.029

    Article  Google Scholar 

  22. Sheikhfaal, S., Angizi, S., Sarmadi, S., Moaiyeri, M.H., Sayedsalehi, S.: Designing efficient QCA logical circuits with power dissipation analysis. Microelectron. J. 46(6), 462–471 (2015)

    Article  Google Scholar 

  23. Silva, D.S., Sardinha, L.H.B., Vieira, M.A.M., Vieira, L.F.M., Vilela Neto, O.P.: Robust serial nanocommunication with QCA. IEEE Trans. Nanotechnol. 14(3), 464–472 (2015)

    Article  Google Scholar 

  24. Das, J.C., De, D.: Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication. Front. Inf. Technol. Electron. Eng. 17(3), 224–236 (2016)

    Article  Google Scholar 

  25. Ahmad, F., Bhat, G.M., Khademolhosseini, H., Azimi, S., Angizi, S., Navi, K.: Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells. J. Comput. Sci. 16, 8–15 (2016)

    Article  MathSciNet  Google Scholar 

  26. Chabi, A.M., et al.: Towards ultra-efficient QCA reversible circuits. Microprocess. Microsyst. 49, 127–138 (2017)

    Article  Google Scholar 

  27. Mano, M., Ciletti, M.D.: Digital Design, vol. 4. Prentice Hall, Upper Saddle River (2006)

    Google Scholar 

  28. Liu, W., Srivastava, S., Lu, L., Orneill, M., Swartzlander, E.E.: Are QCA cryptographic circuits resistant to power analysis attack? IEEE Trans. Nanotechnol. 11(6), 1239–1251 (2012)

    Article  Google Scholar 

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  1. Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran

    Ali Norouzi & Saeed Rasouli Heikalabad

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  1. Ali Norouzi
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  2. Saeed Rasouli Heikalabad
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Correspondence to Saeed Rasouli Heikalabad.

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Norouzi, A., Heikalabad, S.R. Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata. Photon Netw Commun 38, 231–243 (2019). https://doi.org/10.1007/s11107-019-00850-2

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  • DOI: https://doi.org/10.1007/s11107-019-00850-2

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