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High-Visibility Debug-By-Design for FPGA Platforms

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Abstract

The true measure of a general-purpose FPGA platform is user design productivity, not just raw hardware performance. User productivity is a function of several interdependent components of the design environment: system firmware, simulation models, debugging support, device drivers, APIs and so forth. The careful, coordinated design of these components determines the level of debugging visibility and, ultimately, the ease of development for the end user. This paper examines the innovative aspects of the development of the SLAAC FPGA platforms and programming environment. Several novel techniques are presented, including circuit designs for transparent clock stepping and host access to on-board memories; device driver strategies and a “register compiler” to ease the design and testing of the hardware-software interface; and a co-simulation approach for advanced debugging of firmware, device drivers and user applications.

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Correspondence to Peter Bellows.

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Effort sponsored by the Defense Advanced Research Projects Agency (DARPA) and Rome Laboratory, Air Force Material Command, USAF, under agreement number F30602-97-1-0222. The U.S. Government is authorized to reproduce and distribute reprints for governmental purposes notwithstanding any copyright annotation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Defense Advanced Research Projects Agency (DARPA), Rome Laboratory, or the U.S. Government

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Bellows, P. High-Visibility Debug-By-Design for FPGA Platforms. J Supercomput 32, 105–118 (2005). https://doi.org/10.1007/s11227-005-0287-y

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  • DOI: https://doi.org/10.1007/s11227-005-0287-y

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