Skip to main content
Log in

Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

In fault-tolerant multistage interconnection design, the method of providing disjoint paths can tolerate faults, but it is complicated and hard to choose a collision-free path in disjoint paths networks. A network with disjoint paths can concurrently send more identical packets from the source node to increase the arrival ratio or backtrack a packet to the source and take the other disjoint path, but these two methods might increase the collision ratio. In contrast, a dynamic rerouting method finds an alternative path that tolerates faults or prevents collisions. In this paper, we present methods of designing dynamic rerouting networks. This paper presents (1) three design schemes of dynamic rerouting networks to tolerate faults and prevent collisions; (2) design schemes that enable a dynamic rerouting network to use destination tag routing to save hardware cost in switches for computing rerouting tags; (3) a method to prevent a packet from re-encountering the faulty element again after rerouting to reduce the number of rerouting hops and improve the arrival ratio; and (4) simulation results of related dynamic rerouting networks to realize the factors which influence the arrival ratio including the fault tolerant capability and the number of rerouting hops. According to our proposed design schemes and according to our analysis and simulation results, a designer can choose an applicable dynamic rerouting network by using cost-efficient considerations.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Feng TY (1981) A survey of interconnection networks. IEEE Comput 14:12–27

    Google Scholar 

  2. Adams GB III, Agrawal DP, Siegel HJ (1987) A survey and comparison of fault-tolerant multistage interconnection networks. IEEE Trans Comp 20(6):14–27

    Google Scholar 

  3. Stunkel CB, Shea DG, Grice DG, Hochschid PH, Tsao M (1994) The SP1 high-performance switch. In: Proceedings of the Scalable High Performance Computing Conference. Knoxville, TN

  4. Stunkel CB, Shea DG, Abali B, Atkins MG, Bender CA, Grice DG, Hochschild P, Joseph DJ, Nathanson BJ, Swetz RA, Stucke RF, Tsao M, Varker PR (1995) The SP2 high-performance switch. IBM Syst J 34(2):185–204

    Article  Google Scholar 

  5. Chen CW, Ku CJ, Chang CH (2005) Design schemes and performance analysis of dynamic rerouting interconnection networks for tolerating faults. In: Proceedings of The Third International Symposium on Parallel and Distributed Processing and Applications (ISPA’2005), vol 3758, pp 168–179

  6. Yoon K, Hegazy W (1988) The extra stage gamma network. IEEE Trans Comput 37(11):1445–1450

    Article  MATH  Google Scholar 

  7. Chuang PJ (1996) CGIN: A fault tolerant modified gamma interconnection network. IEEE Transactions on Parallel and Distributed Systems 7(12):1301–1306

    Article  Google Scholar 

  8. Seo SW, Feng TY (1995) The composite banyan network. IEEE Trans Parallel Distrib Syst 6(10):1043–1054

    Article  Google Scholar 

  9. Chuang PJ (1998) Creating a highly reliable modified gamma interconnection network using a balance approach. IEE Proc Comput Digital Tech 145(1):27–32

    Article  Google Scholar 

  10. Chen CW, Lu NP, Chung CP (2003) 3-Disjoint gamma interconnection networks. J Syst Soft. 66(2):129–134

    Article  Google Scholar 

  11. Chen CW, Lu NP, Chen TF, Chung CP (2000) Fault—Tolerant gamma interconnection networks by chaining. IEE Proc Comp. Digital Tech 147(2):75–80

    Article  Google Scholar 

  12. Parker DS, Raghavendra CS (1984) The gamma network. IEEE Trans on Comput C-33:367–373

    Google Scholar 

  13. Lee KY, Yoon H (1990) The B-network: A multistage interconnection network with backward links. IEEE Trans on Comput 39(7):966–969

    Article  Google Scholar 

  14. Tzeng NF, Yew PC, Zhu CQ (1988) Realizing fault-tolerant interconnection networks via chaining. IEEE Trans on Computers 37(4):458–462

    Article  Google Scholar 

  15. McMillen RJ, Siegel HJ (1982) Performance and fault tolerance improvements in the inverse augmented data manipulator network. 9th Symp. Computer Architecture, pp. 63–72

  16. Chen CW, Chung CP (2005) Designing a disjoint paths interconnection network with fault tolerance and collision solving. J Supercomput 34(1):63–80

    Article  Google Scholar 

  17. Rau D, Fortes JAB, Siegel HJ (1992) Destination tag routing techniques based on a state model for the IADM network. IEEE Trans Comp. 41(3):274–285

    Article  Google Scholar 

  18. Pease MC III (1977) The indirect binary n-cube microprocessor array. IEEE Trans Comp. C-26:458–473

    Google Scholar 

  19. Wu CL, Feng TY (1980) On a class of multistage interconnection networks. IEEE Trans Comp. 29:694–702

    MATH  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Ching-Wen Chen.

Additional information

This paper was partially supported by the National Science Council NSC-92-2213-E-324-006- and NSC-94-2213-E-035-050-; and the partial part of the preliminary version of this paper was published by the conference ISPA 2005 [5].

Rights and permissions

Reprints and permissions

About this article

Cite this article

Chen, CW. Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions. J Supercomput 38, 307–326 (2006). https://doi.org/10.1007/s11227-006-8784-1

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-006-8784-1

Keywords

Navigation