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Efficient parallel processing with spin-wave nanoarchitectures

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Abstract

In this paper, we study the algorithm design aspects of three newly developed spin-wave architectures. The architectures are capable of simultaneously transmitting multiple signals using different frequencies, and allow for concurrent read/write operations. Using such features, we show a number of parallel and fault-tolerant routing schemes and introduce a set of generic parallel processing techniques that can be used for design of fast algorithms on these spin-wave architectures. We also present a set of application examples to illustrate the operation of the proposed generic parallel techniques.

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Article Open access 05 August 2022

Roman Rietsche, Christian Dremel, … Jan-Marco Leimeister

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Authors and Affiliations

  1. Arent Fox LLP and Electrical Engineering Dept., University of California, Los Angeles, USA

    Mary M. Eshaghian-Wilner

  2. Broadcom Corporation, and Electrical Engineering Dept., University of California, Los Angeles, USA

    Shiva Navab

Authors
  1. Mary M. Eshaghian-Wilner
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  2. Shiva Navab
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Correspondence to Mary M. Eshaghian-Wilner.

Additional information

Authors are listed in alphabetical order. The preliminary version of this paper was presented at the WORLDCOM’07, Las Vegas, June 2007.

Mary M. Eshaghian-Wilner is a Patent Agent at Arent Fox, LLP. She is also an Adjunct Professor of Electrical Engineering at the University of California, Los Angeles.

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Eshaghian-Wilner, M.M., Navab, S. Efficient parallel processing with spin-wave nanoarchitectures. J Supercomput 49, 248–267 (2009). https://doi.org/10.1007/s11227-008-0237-6

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  • DOI: https://doi.org/10.1007/s11227-008-0237-6

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