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Reliable network-on-chip design for multi-core system-on-chip

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Abstract

Network-on-chip (NoC) architectures must deliver good latency-through put performance in the face of tight power and area budgets. However, in high-performance chip design, a significant design challenge is how to fulfill the requirements of circuit noise elimination, since the faults will slow down performance and dissipate much of the overall system power. This paper presents a simple coding scheme for reducing power dissipation, crosstalk noise, and crosstalk delay on the bus while simultaneously detecting errors at runtime. It uses a simple bus-invert encoding technique to reduce the prohibited transitions in terms of crosstalk noise and power dissipation. We also design a corresponding detector to detect errors at the input of the NoC routers. It can save energy by interrupting communications without storing and routing the packets when errors occur during transmissions. The experimental results for various multimedia applications show significant reduction in the number of patterns that are most likely to produce crosstalk errors. The results also show that it is attractive in terms of cost to apply the detecting logic to routers in the NoC with respect to the power consumption.

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  1. Kuei-Chung Chang

    Present address: , No. 100 Wenhwa Rd., Seatwen, Taichung City, Taiwan, 40724, ROC

Authors and Affiliations

  1. Department of Information Engineering and Computer Science, Feng Chia University, Taichung City, Taiwan, ROC

    Kuei-Chung Chang

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  1. Kuei-Chung Chang
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Correspondence to Kuei-Chung Chang.

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Chang, KC. Reliable network-on-chip design for multi-core system-on-chip. J Supercomput 55, 86–102 (2011). https://doi.org/10.1007/s11227-009-0376-4

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  • DOI: https://doi.org/10.1007/s11227-009-0376-4

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