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On pedagogy of nanometric circuit reliability

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Abstract

Fast-shrinking dimensions of semiconductor devices are expected to reach sub-10 nm scale in a few years. Although smaller in size and lower in power consumption than today’s CMOS devices, the nanoscaled devices are much less reliable due to manufacturing imperfections (hard errors), and noise and radiation-induced faults (soft errors). Consequently, in addition to timing, area, and power, the reliability has to become a new design criterion. This also means that the topic of reliability has to be incorporated into the circuit design curriculum. In this paper, we propose a course on circuit reliability. We also present in detail, an automated tool for calculation of reliability which could be incorporated into the course as a means for active learning.

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References

  1. Beg A, Prasad PWC, Ibrahim W, Shama E (2008) Utilizing synthesis to verify Boolean function models. In Proceedings of IEEE international symposium on circuits and systems, Seattle, WA, USA, pp 1576–1579

  2. Constantinescu C (2003) Trends and challenges in VLSI circuit reliability. IEEE Micro 32(4):14–19

    Article  Google Scholar 

  3. Dai J, Wang L, Jain F (2007) Analysis of defect tolerance in molecular electronics using information-theoretic measures. In Proceedings of IEEE international symposium on nanoscale architecture, San Jose, CA, USA, pp 21–26

  4. Feldkamp U, Niemeyer CM (2006) Rational design of DNA nanoarchitectures. Angew Chem Int Ed 45(13):1856–1876

    Article  Google Scholar 

  5. Garzia M, Hudepohl J, Snipes W, Lyu M, Musa J, Smidts C, et al (2006) How should software reliability engineering (SRE) be taught? ACM SIGSOFT Softw Eng Notes 31(4):1–5

    Article  Google Scholar 

  6. Green JE, Choi JW, Boukai A, Bunimovich Y, Johnston-Halperin E, DeIonno EY et al (2007) A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimeter. Nature 445(25): 414–417

    Article  Google Scholar 

  7. Kamoua R, Kim D, Roach G (2006) Incorporating nanoscale system design into the undergraduate electrical and computer engineering curriculum. In Proceedings of the international conference on engineering education, San Juan, Puerto Rico, pp M4K4–M4K9

  8. Kim D, Kamoua R, Pacelli A (2005) Design-oriented introduction of nanotechnology into the electrical and computer engineering curriculum. J Educ Technol Syst 34(2):155–164

    Article  MATH  Google Scholar 

  9. Krishnaswamy G, Viamontes G, Markov I, Hayes JP (2005) Accurate reliability evaluation and enhancement via probabilistic transfer matrices. In Proceedings of design, automation & test in Europe, Munich, Germany, pp 282–287

  10. Krishnaswamy S, Plaza SM, Markov IL, Hayes JP (2007) Enhancing design robustness with reliability-aware resynthesis and logic simulation. In Proceedings of IEEE/ACM international conference on computer-aided design, San Jose, CA, USA, pp 149–154

  11. Krishnaswamy S, Plaza SM, Hayes JP (2007) Tracking uncertainty with probabilistic logic circuit testing. IEEE Des Test Comput 24(4):312–321

    Article  Google Scholar 

  12. Li H, Mundy J, Patterson W, Kazazis D, Zaslavsky A, Bahar RI (2007) Thermally-induced soft errors in nanoscale CMOS circuits. In Proceedings of IEEE international symposium on nanoscale architecture, San Jose, CA, USA, pp 62–69

  13. Likharev KK (1999) Single-electron devices and their applications. Proc IEEE 87(4):606–632

    Article  Google Scholar 

  14. Lyu MR (2007) Software reliability engineering: a roadmap. In Proceedings of the international conference on software engineering, Washington, DC, USA, pp 153–170

  15. Martorell F, Cotofana SD, Rubio A (2008) An analysis of internal parameter variations effects on nanoscaled gates. IEEE Trans Nanotechnol 7(1):24–33

    Article  Google Scholar 

  16. Mayers AW, Kurtz SK (2000) Teaching reliability engineering to working engineers. In Proceedings of frontiers in education conference, Kansas City, MO, USA, pp F2E/14–F2E/19

  17. Meindl JD, Chen Q, Davis JA (2001) Limits on silicon nanoelectronics for terascale integration. Science 293(14):2044–2049

    Article  Google Scholar 

  18. Mohanram K, Touba NA (2003) Cost-effective approach for reducing soft error failure rate in logic circuits. In Proceedings of the international test conference, Charlotte, NC, USA, pp 893–901

  19. Nicolić K, Sadek A, Forshaw M (2001) Architecture for reliable computing with unreliable nanodevices. In Proceedings of the IEEE conference on nanotechnology, Maui, HI, USA, pp 254–259

  20. Patel KN, Markov IL, Hayes JP (2003) Evaluating circuit reliability under probabilistic gate-level fault models. In Proceedings of the international workshop on logic synthesis, Laguna Beach, CA, USA, pp 59–64

  21. Semiconductor Industry Association (2006) International technology roadmap for semiconductor (ITRS), SEMATECH, Austin, TX, USA

  22. Sivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L (2002) Modeling the effect of technology trends on soft error rate of combinatorial logic. In Proceedings of the international conference on dependable systems & networks, Washington, DC, USA, pp 389–398

  23. Tosun S, Mansouri N, Arvasm E, Kandemir M, Xie Y, Hung W-L (2005) Reliability-centric hardware/software co-design. In Proceedings of the international symposium on quality electronic design, San Jose, CA, USA, pp 375–380

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  1. College of Information Technology, UAE University, P.O. Box 17551, Al-Ain, Abu Dhabi, UAE

    Azam Beg

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  1. Azam Beg
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Correspondence to Azam Beg.

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Beg, A. On pedagogy of nanometric circuit reliability. J Supercomput 59, 762–778 (2012). https://doi.org/10.1007/s11227-010-0471-6

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  • DOI: https://doi.org/10.1007/s11227-010-0471-6

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