Abstract
Communication plays a critical role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. As regular NoC topologies are infeasible to satisfy the performance demand for application-specific NoC, customized topology synthesis is therefore desirable. However, NoC topology synthesis problem is an NP-hard problem. In this paper, we propose a suboptimal genetic-algorithm based technique to synthesize application-specific NoC topology with system-level floorplan awareness. The method minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We have evaluated the proposed technique by running a number of representative benchmark applications and the results indicate that our method generates approximate optimal topologies effectively and efficiently for all benchmarks under consideration.
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Lai, G., Lin, X. Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique. J Supercomput 61, 418–437 (2012). https://doi.org/10.1007/s11227-011-0599-z
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DOI: https://doi.org/10.1007/s11227-011-0599-z