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Power-aware register assignment for large register file design

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Abstract

The design trend of high-speed microprocessors is toward wider and wider issue architecture to increase instruction-level parallelism. Such architecture needs a large register file to reduce register pressure. A large register file, however, consumes much more power during program execution. In this paper, we first analyze the register requirements in general programs, especially among those parts of the program which take most of execution time. Next, we drive a power-aware register assignment algorithm to distribute different access-frequencies temporary values over different register groups. Finally, we design a dynamic voltage scaling circuit to save the power consumption for those infrequently accessed registers. Experimental results show that partitioning the storage locations of temporary values in a register file will indeed impact the utilization of each register, and within a DVS approach a large register file can thus save a significant ratio of power consumption.

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Authors and Affiliations

  1. Department of Computer Science and Information Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan, Taiwan

    Wann-Yun Shieh & Bo-Syun Wang

Authors
  1. Wann-Yun Shieh
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  2. Bo-Syun Wang
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Correspondence to Wann-Yun Shieh.

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Shieh, WY., Wang, BS. Power-aware register assignment for large register file design. J Supercomput 61, 719–742 (2012). https://doi.org/10.1007/s11227-011-0633-1

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  • DOI: https://doi.org/10.1007/s11227-011-0633-1

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