Abstract
With the development of the semiconductor technology, more processors can be integrated onto a single chip. Network-on-Chip is an efficient communication solution for many-core system. However, enhancing performance with lower energy consumption is still a challenge. One critical issue is mapping applications to NoC. This work proposed an online mapping method, which optimizes task mapping algorithm to reduce communication energy consumption. The communication status of applications at runtime is analyzed first. Then, the algorithm computes the mapping placement dynamically and implements the real-time mapping online. Experimental results based on simulation show that the algorithm proposed in this article can achieve more than 20% communication energy saving compared with first fit mapping and nearest neighbor mapping. The migration cost caused by the remapping process is also considered, and can be calculated at the runtime to estimate the effect of remapping.
Similar content being viewed by others
References
Barcelos D, Brião EW, Wagner F (2007) A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs. In: Proceedings of the 20th annual conference on integrated circuits and systems design, 2007, pp 282–287
Bertozzi S, Acquaviva A, Bertozzi D, Poggiali A (2006) Supporting task migration in multi-processor systems-on-chip: a feasibility study. In: Proceedings of the conference on design, automation and test in Europe, 2006, pp 15–20
Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. ACM Comput Surv 38(1). doi:10.1145/1132952.1132953
Briao EW, Barcelos D, Wronski F, Wagner FR (2007) Impact of task migration in NoC-based MPSoCs for soft real-time applications. In: IFIP international conference on very large scale integration, 2007, pp 296–299
Chang K-C, Shen J-S, Chen T-F (2008) Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. ACM Trans Des Autom Electron Syst 13(1):12:1–12:31
Chen G, Li F, Son SW, Kandemir M (2008) Application mapping for chip multiprocessors. In: Proceedings of the 45th annual design automation conference, 2008, pp 620–625
Chou C-L, Marculescu R (2007) Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels. In: Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis, 2007, pp 161–166
Chou C-L, Marculescu R (2008) User-aware dynamic task allocation in networks-on-chip. In: Proceedings of the conference on design, automation and test in Europe, 2008, pp 1232–1237
Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th annual design automation conference, 2001, pp 684–689
Dally W, Towles B (2003) Principles and practices of interconnection networks. Morgan Kaufmann, San Francisco
Hu J, Marculescu R (2004) Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: Proceedings of the conference on design, automation and test in Europe, vol 1, 2004, pp. 10234
Kahng AB, Li B, Peh L-S, Samadi K (2009) ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: Proceedings of the conference on design, automation and test in Europe, 2009, pp. 423–428
Kumar S, Jantsch A, Soininen J-P, Forsell M, Millberg M, Oberg J, Tiensyrja K, Hemani A (2002) A network on chip architecture and design methodology. In: Proceedings of IEEE computer society annual symposium on VLSI, 2002, pp 105–112
Liu A-H, Dick RP (2006) Automatic run-time extraction of communication graphs from multithreaded applications. In: Proceedings of the 4th international conference on hardware/software codesign and system synthesis, 2006, pp 46–51
Mahadevan S, Angiolini F, Storgaard M, Olsen RG, Sparso J, Madsen J (2005) A network traffic generator model for fast network-on-chip simulation. In: Proceedings of the conference on design, automation and test in Europe, vol 2, 2005, pp 780–785
Marculescu R, Bogdan P (2007) The chip is the network: toward a science of network-on-chip design. In: Foundations and trends in electronic design automation, vol 2, 2007, pp 371–461
Marculescu R, Ogras UY, Peh L-S, Jerger NE, Hoskote Y (2009) Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(1):3–21
Peh L-S, Jerger NE (2009) On-chip networks. Morgan and Claypool, San Rafael
Sanchez D, Michelogiannakis G, Kozyrakis C (2010) An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans Archit Code Optim 7(1):4:1–4:28
Sehgal VK, Chauhan DS (2009) State observer controller design for packets flow control in networks-on-chip. J Supercomput 54:1–32
Ye TT, De Micheli G, Benini L (2002) Analysis of power consumption on switch fabrics in network routers. In: Proceedings of the 39th annual design automation conference, 2002, pp V524–529
Noxim (2010) http://www.noxim.org. Accessed 25 December 2010
Simics (2010) http://www.virtutech.com/products. Accessed 25 December 2010
Author information
Authors and Affiliations
Corresponding authors
Rights and permissions
About this article
Cite this article
Xie, B., Chen, T., Hu, W. et al. An energy-aware online task mapping algorithm in NoC-based system. J Supercomput 64, 1021–1037 (2013). https://doi.org/10.1007/s11227-011-0678-1
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11227-011-0678-1