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A tagless cache design for power saving in embedded systems

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Abstract

In embedded systems, cache is commonly used to improve system performance. However, the cache consumes a large amount of power, and among the components of the cache memory, tag comparisons consume the most amount of power. Therefore, how to design a cache that does not consume so much power when comparing tags and that has a high hit ratio is an important challenge. In this paper, we propose a Tagless Instruction Cache, called TL-IC, that does not perform tag comparisons in order to save power in embedded systems. To guarantee that an instruction fetched from TL-IC is the desired instruction, instead of cache lines being used, the basic blocks of programs are placed into TL-IC. In addition, to utilize TL-IC as much as possible in order to save the most amount of power and to take into account the general-purpose and special-purpose applications, both the static allocation and the dynamic allocation of basic blocks are used to select the frequently executed basic blocks of programs in TL-IC. With a high utilization of TL-IC that does not perform tag comparisons, the power consumed in fetching instructions can be efficiently reduced. In the simulation results, we show and compare the power consumption of our proposed TL-IC, L0 cache, Linebuffer, and TH-IC.

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Authors and Affiliations

  1. Department of Information Engineering and Computer Science, Feng Chia University, Taichung City, 40724, Taiwan

    Ching-Wen Chen & Chang-Jung Ku

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  1. Ching-Wen Chen
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  2. Chang-Jung Ku
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Correspondence to Ching-Wen Chen.

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Chen, CW., Ku, CJ. A tagless cache design for power saving in embedded systems. J Supercomput 62, 174–198 (2012). https://doi.org/10.1007/s11227-011-0694-1

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