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A star network approach in heterogeneous multiprocessors system on chip

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Abstract

Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA.

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Acknowledgements

This work was supported by a grant from Jiangsu provincial Natural Science Foundation “Study of Task Parallelization on Service-oriented Heterogeneous Reconfigurable Multiprocessor System-on-chip”, and Jiangsu production-teaching-research joint innovation project (No. BY2009128). This paper has benefited from generous support and help from many sources. The authors would like to also express their deepest gratitude to Professor Jim Martin, Oliver Diessel, Ray Cheung, the reviewers, and editors for their valuable comments and suggestions that helped to improve this manuscript.

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Authors and Affiliations

  1. School of Computer Science, University of Science and Technology of China, Hefei, Anhui, China

    Chao Wang & Junneng Zhang

  2. Suzhou Institute of USTC, University of Science and Technology of China, Suzhou, Jiangsu, China

    Xi Li, Xuehai Zhou & Aili Wang

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  1. Chao Wang
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Correspondence to Chao Wang.

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Wang, C., Li, X., Zhang, J. et al. A star network approach in heterogeneous multiprocessors system on chip. J Supercomput 62, 1404–1424 (2012). https://doi.org/10.1007/s11227-012-0810-x

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