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Dual-mode inter-router communication channel for deflection-routed networks-on-chip

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Abstract

Deflection routing, characterized by routing simplicity and minimal in-router buffer resources, has recently emerged as a promising approach for improving power and area efficiency of on-chip networks. With this routing strategy, packet contentions in routers are resolved by intentionally misrouting some of packets along unwanted directions instead of storing them. However, at higher network loads, when the contentions are more frequent, packets take longer paths on average to their destinations, and thus increase the energy consumption, delay, and reduce the throughput in the network. To address this problem, we enhance the inter-router communication channels with a lightweight link-control mechanism that prevents unnecessary network hops by forcing deflected packets, when possible, to loop back to their current routers instead of being misrouted. The effect of the packet loop-backing is similar to that of storing deflected packet into a small central in-router buffer, but is accomplished with lower implementation cost (i.e. there is no need for additional buffer memory) and without any modification to the underlying router microarchitecture. Evaluations on synthetic traffic patterns show that the proposed misrouting suppression mechanism yields an improvement of 11.8–14.5 % in network saturation throughput when coupled with the conventional bufferless and buffered deflection-based routers.

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Acknowledgments

This work was partially supported by the Serbian Ministry of Science and Technological Development Project No. TR-32009, TR-33035.

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Authors and Affiliations

  1. Faculty of Electronic Engineering, University of Nis, A. Medvedeva 14, 18000, Nis, Serbia

    Igor Z. Stojanovic, Milica D. Jovanovic & Goran Lj. Djordjevic

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  1. Igor Z. Stojanovic
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  2. Milica D. Jovanovic
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  3. Goran Lj. Djordjevic
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Correspondence to Igor Z. Stojanovic.

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Stojanovic, I.Z., Jovanovic, M.D. & Djordjevic, G.L. Dual-mode inter-router communication channel for deflection-routed networks-on-chip. J Supercomput 71, 2597–2613 (2015). https://doi.org/10.1007/s11227-015-1407-y

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