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Joint frequency scaling of processor and DRAM

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Abstract

Energy efficiency and energy-proportional computing have become a central focus in modern supercomputers. Many previous energy-saving strategies have focused solely on the CPU while the DRAM subsystem has not been addressed sufficiently, even though memory consumes about 20 % of the total power in a typical server platform. This paper describes a novel runtime system that scales the frequency of both processor and DRAM-based on the performance and power models, also proposed here. Specifically, first, a performance-loss constraint is chosen for an application, then, an optimal processor–DRAM frequency pair is modeled such that the pair minimizes the energy consumption in a given timeslice. Experiments performed on SPEC CPU™ 2006, NAS NPB, and pARMS benchmarks demonstrate that the proposed runtime system may obtain total energy savings both for memory- and compute-intensive applications. In particular, as much as 22 % of energy was saved with a low performance loss of about 4.8 %.

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Notes

  1. TOP500 list: http://top500.org/.

  2. Authors’ previous work [31] outlines the pitfalls of the models relying on the user-defined performance-loss tolerance and introduces a model based on instantaneous power consumption.

  3. LMBench web-site: http://www.bitmover.com/lmbench/.

  4. See, e.g., http://www.anandtech.com/show/6355/intels-haswell-architecture/8.

  5. Wattsup meter: https://www.wattsupmeters.com.

  6. SPEC CPU™ 2006 benchmarks web-site: https://www.spec.org/cpu2006/.

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Acknowledgments

This work was supported in part by the Air Force Office of Scientific Research under the AFOSR award FA9550-12-1-0476, by the National Science Foundation grants 0904782, 1047772, 1516096, by the US Department of Energy, Office of Advanced Scientific Computing Research, through the Ames Laboratory, operated by Iowa State University under contract No. DE-AC02-07CH11358, and by the US Department of Defense High Performance Computing Modernization Program, through a HASI grant.

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Authors and Affiliations

  1. ODU Research Foundation, Norfolk, USA

    Vaibhav Sundriyal

  2. Old Dominion University, Norfolk, USA

    Masha Sosonkina

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  1. Vaibhav Sundriyal
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  2. Masha Sosonkina
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Correspondence to Vaibhav Sundriyal.

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Sundriyal, V., Sosonkina, M. Joint frequency scaling of processor and DRAM. J Supercomput 72, 1549–1569 (2016). https://doi.org/10.1007/s11227-016-1680-4

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